URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_Default/] [DE0_NANO_SOC_Default.v] - Blame information for rev 221

Details | Compare with Previous | View Log


 
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================
 
//`define ENABLE_HPS
module DE0_NANO_SOC_Default(
 
        //////////// ADC //////////
        output                                  ADC_CONVST,
        output                                  ADC_SCK,
        output                                  ADC_SDI,
        input                                   ADC_SDO,
        //////////// CLOCK //////////
        input                                   FPGA_CLK1_50,
        input                                   FPGA_CLK2_50,
        input                                   FPGA_CLK3_50,
 
`ifdef ENABLE_HPS
        //////////// HPS //////////
        inout                                   HPS_CONV_USB_N,
        output              [14:0]               HPS_DDR3_ADDR,
        output               [2:0]               HPS_DDR3_BA,
        output                                  HPS_DDR3_CAS_N,
        output                                  HPS_DDR3_CK_N,
        output                                  HPS_DDR3_CK_P,
        output                                  HPS_DDR3_CKE,
        output                                  HPS_DDR3_CS_N,
        output               [3:0]               HPS_DDR3_DM,
        inout               [31:0]               HPS_DDR3_DQ,
        inout                [3:0]               HPS_DDR3_DQS_N,
        inout                [3:0]               HPS_DDR3_DQS_P,
        output                                  HPS_DDR3_ODT,
        output                                  HPS_DDR3_RAS_N,
        output                                  HPS_DDR3_RESET_N,
        input                                   HPS_DDR3_RZQ,
        output                                  HPS_DDR3_WE_N,
        output                                  HPS_ENET_GTX_CLK,
        inout                                   HPS_ENET_INT_N,
        output                                  HPS_ENET_MDC,
        inout                                   HPS_ENET_MDIO,
        input                                   HPS_ENET_RX_CLK,
        input                [3:0]               HPS_ENET_RX_DATA,
        input                                   HPS_ENET_RX_DV,
        output               [3:0]               HPS_ENET_TX_DATA,
        output                                  HPS_ENET_TX_EN,
        inout                                   HPS_GSENSOR_INT,
        inout                                   HPS_I2C0_SCLK,
        inout                                   HPS_I2C0_SDAT,
        inout                                   HPS_I2C1_SCLK,
        inout                                   HPS_I2C1_SDAT,
        inout                                   HPS_KEY,
        inout                                   HPS_LED,
        inout                                   HPS_LTC_GPIO,
        output                                  HPS_SD_CLK,
        inout                                   HPS_SD_CMD,
        inout                [3:0]               HPS_SD_DATA,
        output                                  HPS_SPIM_CLK,
        input                                   HPS_SPIM_MISO,
        output                                  HPS_SPIM_MOSI,
        inout                                   HPS_SPIM_SS,
        input                                   HPS_UART_RX,
        output                                  HPS_UART_TX,
        input                                   HPS_USB_CLKOUT,
        inout                [7:0]               HPS_USB_DATA,
        input                                   HPS_USB_DIR,
        input                                   HPS_USB_NXT,
        output                                  HPS_USB_STP,
`endif /*ENABLE_HPS*/
 
        //////////// KEY //////////
        input                [1:0]               KEY,
 
        //////////// LED //////////
        output               [7:0]               LED,
 
        //////////// SW //////////
        input                [3:0]               SW,
 
        //////////// GPIO_0, GPIO connect to GPIO Default //////////
        inout               [35:0]               GPIO_0,
 
        //////////// GPIO_1, GPIO connect to GPIO Default //////////
        inout               [35:0]               GPIO_1
);
 
//=======================================================
//  REG/WIRE declarations
//=======================================================
reg  [31:0]      Cont;
 
//=======================================================
//  Structural coding
//=======================================================
 
assign GPIO_0           =       36'hzzzzzzzz;
assign GPIO_1           =       36'hzzzzzzzz;
 
always@(posedge FPGA_CLK1_50 or negedge KEY[0])
    begin
        if(!KEY[0])
                         Cont   <=      0;
        else
                         Cont   <=      Cont+1;
    end
 
assign  LED =   KEY[0]? {Cont[25:24],Cont[25:24],Cont[25:24],
                             Cont[25:24],Cont[25:24]}:10'h3ff;
 
endmodule

Line No.	Rev	Author	Line
1	221	olivier.gi
2			`//=======================================================`
3			`// This code is generated by Terasic System Builder`
4			`//=======================================================`
5
6			//`define ENABLE_HPS
7			`module DE0_NANO_SOC_Default(`
8
9			`//////////// ADC //////////`
10			`output ADC_CONVST,`
11			`output ADC_SCK,`
12			`output ADC_SDI,`
13			`input ADC_SDO,`
14			`//////////// CLOCK //////////`
15			`input FPGA_CLK1_50,`
16			`input FPGA_CLK2_50,`
17			`input FPGA_CLK3_50,`
18
19			`ifdef ENABLE_HPS
20			`//////////// HPS //////////`
21			`inout HPS_CONV_USB_N,`
22			`output [14:0] HPS_DDR3_ADDR,`
23			`output [2:0] HPS_DDR3_BA,`
24			`output HPS_DDR3_CAS_N,`
25			`output HPS_DDR3_CK_N,`
26			`output HPS_DDR3_CK_P,`
27			`output HPS_DDR3_CKE,`
28			`output HPS_DDR3_CS_N,`
29			`output [3:0] HPS_DDR3_DM,`
30			`inout [31:0] HPS_DDR3_DQ,`
31			`inout [3:0] HPS_DDR3_DQS_N,`
32			`inout [3:0] HPS_DDR3_DQS_P,`
33			`output HPS_DDR3_ODT,`
34			`output HPS_DDR3_RAS_N,`
35			`output HPS_DDR3_RESET_N,`
36			`input HPS_DDR3_RZQ,`
37			`output HPS_DDR3_WE_N,`
38			`output HPS_ENET_GTX_CLK,`
39			`inout HPS_ENET_INT_N,`
40			`output HPS_ENET_MDC,`
41			`inout HPS_ENET_MDIO,`
42			`input HPS_ENET_RX_CLK,`
43			`input [3:0] HPS_ENET_RX_DATA,`
44			`input HPS_ENET_RX_DV,`
45			`output [3:0] HPS_ENET_TX_DATA,`
46			`output HPS_ENET_TX_EN,`
47			`inout HPS_GSENSOR_INT,`
48			`inout HPS_I2C0_SCLK,`
49			`inout HPS_I2C0_SDAT,`
50			`inout HPS_I2C1_SCLK,`
51			`inout HPS_I2C1_SDAT,`
52			`inout HPS_KEY,`
53			`inout HPS_LED,`
54			`inout HPS_LTC_GPIO,`
55			`output HPS_SD_CLK,`
56			`inout HPS_SD_CMD,`
57			`inout [3:0] HPS_SD_DATA,`
58			`output HPS_SPIM_CLK,`
59			`input HPS_SPIM_MISO,`
60			`output HPS_SPIM_MOSI,`
61			`inout HPS_SPIM_SS,`
62			`input HPS_UART_RX,`
63			`output HPS_UART_TX,`
64			`input HPS_USB_CLKOUT,`
65			`inout [7:0] HPS_USB_DATA,`
66			`input HPS_USB_DIR,`
67			`input HPS_USB_NXT,`
68			`output HPS_USB_STP,`
69			`endif /ENABLE_HPS/
70
71			`//////////// KEY //////////`
72			`input [1:0] KEY,`
73
74			`//////////// LED //////////`
75			`output [7:0] LED,`
76
77			`//////////// SW //////////`
78			`input [3:0] SW,`
79
80			`//////////// GPIO_0, GPIO connect to GPIO Default //////////`
81			`inout [35:0] GPIO_0,`
82
83			`//////////// GPIO_1, GPIO connect to GPIO Default //////////`
84			`inout [35:0] GPIO_1`
85			`);`
86
87			`//=======================================================`
88			`// REG/WIRE declarations`
89			`//=======================================================`
90			`reg [31:0] Cont;`
91
92			`//=======================================================`
93			`// Structural coding`
94			`//=======================================================`
95
96			`assign GPIO_0 = 36'hzzzzzzzz;`
97			`assign GPIO_1 = 36'hzzzzzzzz;`
98
99			`always@(posedge FPGA_CLK1_50 or negedge KEY[0])`
100			`begin`
101			`if(!KEY[0])`
102			`Cont <= 0;`
103			`else`
104			`Cont <= Cont+1;`
105			`end`
106
107			`assign LED = KEY[0]? {Cont[25:24],Cont[25:24],Cont[25:24],`
108			`Cont[25:24],Cont[25:24]}:10'h3ff;`
109
110			`endmodule`

Browse

Tools

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_Default/] [DE0_NANO_SOC_Default.v] - Blame information for rev 221