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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [my_first_fpga/] [counter_bus_mux.bsf] - Blame information for rev 221

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Line No. Rev Author Line
1 221 olivier.gi
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, the Altera Quartus II License Agreement,
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the Altera MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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devices manufactured by Altera and sold by Altera or its
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authorized distributors.  Please refer to the applicable
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agreement for further details.
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*/
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(header "symbol" (version "1.2"))
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(symbol
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        (rect 0 0 144 80)
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        (text "counter_bus_mux" (rect 22 0 143 16)(font "Arial" (font_size 10)))
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        (text "inst" (rect 8 64 25 76)(font "Arial" ))
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        (port
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                (pt 0 40)
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