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olivier.gi |
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus II License Agreement,
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# the Altera MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 14.1.0 Build 186 12/03/2014 SJ Full Version
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# Date created = 14:07:42 December 24, 2014
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# my_first_fpga_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSEMA4U23C6
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set_global_assignment -name TOP_LEVEL_ENTITY my_first_fpga
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:07:42 DECEMBER 24, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name BDF_FILE my_first_fpga.bdf
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set_global_assignment -name VERILOG_FILE simple_counter.v
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name QIP_FILE pll.qip
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set_global_assignment -name SIP_FILE pll.sip
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set_global_assignment -name QIP_FILE counter_bus_mux.qip
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_location_assignment PIN_V11 -to CLOCK_50
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set_location_assignment PIN_AH16 -to KEY[1]
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set_location_assignment PIN_AH17 -to KEY[0]
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set_location_assignment PIN_V15 -to LED[3]
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set_location_assignment PIN_V16 -to LED[2]
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set_location_assignment PIN_AA24 -to LED[1]
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set_location_assignment PIN_W15 -to LED[0]
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set_global_assignment -name SDC_FILE my_first_fpga.sdc
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set_global_assignment -name ENABLE_OCT_DONE OFF
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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