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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [my_first_fpga/] [output_files/] [my_first_fpga.map.summary] - Blame information for rev 221

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Line No. Rev Author Line
1 221 olivier.gi 
Analysis & Synthesis Status : Successful - Fri Dec 26 09:28:44 2014
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Quartus II 64-Bit Version : 14.1.0 Build 186 12/03/2014 SJ Full Version
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Revision Name : my_first_fpga
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Top-level Entity Name : my_first_fpga
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Family : Cyclone V
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Logic utilization (in ALMs) : N/A
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Total registers : 27
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Total pins : 7
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Total virtual pins : 0
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Total block memory bits : 0
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Total DSP Blocks : 0
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Total HSSI RX PCSs : 0
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Total HSSI PMA RX Deserializers : 0
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Total HSSI TX PCSs : 0
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Total HSSI PMA TX Serializers : 0
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Total PLLs : 1
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Total DLLs : 0

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