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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [my_first_fpga/] [pll.cmp] - Blame information for rev 221

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        component pll is
                port (
                        refclk   : in  std_logic := 'X'; -- clk
                        rst      : in  std_logic := 'X'; -- reset
                        outclk_0 : out std_logic         -- clk
                );
        end component pll;
 

Line No.	Rev	Author	Line
1	221	olivier.gi	`component pll is`
2			`port (`
3			`refclk : in std_logic := 'X'; -- clk`
4			`rst : in std_logic := 'X'; -- reset`
5			`outclk_0 : out std_logic -- clk`
6			`);`
7			`end component pll;`
8

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [my_first_fpga/] [pll.cmp] - Blame information for rev 221