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olivier.gi |
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# (C) 2001-2014 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Altera
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# Program License Subscription Agreement, Altera MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by Altera
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 14.1 186 win32 2014.12.24.17:12:23
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# ----------------------------------------
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# Auto-generated simulation script
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# ----------------------------------------
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# Initialize variables
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if ![info exists SYSTEM_INSTANCE_NAME] {
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set SYSTEM_INSTANCE_NAME ""
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} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
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set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
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}
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if ![info exists TOP_LEVEL_NAME] {
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set TOP_LEVEL_NAME "pll"
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}
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if ![info exists QSYS_SIMDIR] {
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set QSYS_SIMDIR "./../"
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}
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if ![info exists QUARTUS_INSTALL_DIR] {
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set QUARTUS_INSTALL_DIR "C:/altera/14.1/quartus/"
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}
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# ----------------------------------------
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# Initialize simulation properties - DO NOT MODIFY!
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set ELAB_OPTIONS ""
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set SIM_OPTIONS ""
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if ![ string match "*-64 vsim*" [ vsim -version ] ] {
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} else {
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}
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set Aldec "Riviera"
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if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
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set Aldec "Active"
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}
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if { [ string match "Active" $Aldec ] } {
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scripterconf -tcl
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createdesign "$TOP_LEVEL_NAME" "."
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opendesign "$TOP_LEVEL_NAME"
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}
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# ----------------------------------------
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# Copy ROM/RAM files to simulation directory
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alias file_copy {
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echo "\[exec\] file_copy"
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}
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# ----------------------------------------
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# Create compilation libraries
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proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
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ensure_lib ./libraries
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ensure_lib ./libraries/work
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vmap work ./libraries/work
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ensure_lib ./libraries/altera_ver
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vmap altera_ver ./libraries/altera_ver
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ensure_lib ./libraries/lpm_ver
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vmap lpm_ver ./libraries/lpm_ver
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ensure_lib ./libraries/sgate_ver
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vmap sgate_ver ./libraries/sgate_ver
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ensure_lib ./libraries/altera_mf_ver
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vmap altera_mf_ver ./libraries/altera_mf_ver
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ensure_lib ./libraries/altera_lnsim_ver
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vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
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ensure_lib ./libraries/cyclonev_ver
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vmap cyclonev_ver ./libraries/cyclonev_ver
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ensure_lib ./libraries/cyclonev_hssi_ver
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vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
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ensure_lib ./libraries/cyclonev_pcie_hip_ver
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vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
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# ----------------------------------------
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# Compile device library files
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alias dev_com {
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echo "\[exec\] dev_com"
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
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vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
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}
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# ----------------------------------------
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# Compile the design files in correct order
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alias com {
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echo "\[exec\] com"
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vlog "$QSYS_SIMDIR/pll.vo"
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}
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# ----------------------------------------
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# Elaborate top level design
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alias elab {
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echo "\[exec\] elab"
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eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
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}
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# ----------------------------------------
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# Elaborate the top level design with -dbg -O2 option
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alias elab_debug {
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echo "\[exec\] elab_debug"
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eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
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}
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# ----------------------------------------
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# Compile all the design files and elaborate the top level design
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alias ld "
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dev_com
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com
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elab
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"
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# ----------------------------------------
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# Compile all the design files and elaborate the top level design with -dbg -O2
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alias ld_debug "
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dev_com
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com
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elab_debug
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"
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# ----------------------------------------
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# Print out user commmand line aliases
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alias h {
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echo "List Of Command Line Aliases"
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echo
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echo "file_copy -- Copy ROM/RAM files to simulation directory"
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echo
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echo "dev_com -- Compile device library files"
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echo
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echo "com -- Compile the design files in correct order"
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echo
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echo "elab -- Elaborate top level design"
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echo
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echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
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echo
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echo "ld -- Compile all the design files and elaborate the top level design"
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echo
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echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
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echo
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echo
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echo
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echo "List Of Variables"
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echo
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echo "TOP_LEVEL_NAME -- Top level module name."
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echo
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echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
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echo
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echo "QSYS_SIMDIR -- Qsys base simulation directory."
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echo
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echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
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}
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file_copy
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h
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