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olivier.gi |
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# (C) 2001-2014 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Altera
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# Program License Subscription Agreement, Altera MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by Altera
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 14.1 186 win32 2014.12.24.17:12:23
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# ----------------------------------------
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# vcs - auto-generated simulation script
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# ----------------------------------------
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# initialize variables
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TOP_LEVEL_NAME="pll"
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QSYS_SIMDIR="./../../"
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QUARTUS_INSTALL_DIR="C:/altera/14.1/quartus/"
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SKIP_FILE_COPY=0
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SKIP_ELAB=0
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SKIP_SIM=0
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USER_DEFINED_ELAB_OPTIONS=""
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USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
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# ----------------------------------------
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# overwrite variables - DO NOT MODIFY!
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# This block evaluates each command line argument, typically used for
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# overwriting variables. An example usage:
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# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
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for expression in "$@"; do
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eval $expression
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if [ $? -ne 0 ]; then
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echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
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exit $?
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fi
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done
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# ----------------------------------------
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# initialize simulation properties - DO NOT MODIFY!
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ELAB_OPTIONS=""
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SIM_OPTIONS=""
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if [[ `vcs -platform` != *"amd64"* ]]; then
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:
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else
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:
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fi
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# ----------------------------------------
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# copy RAM/ROM files to simulation directory
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vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
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$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
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-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
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$QSYS_SIMDIR/pll.vo \
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-top $TOP_LEVEL_NAME
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# ----------------------------------------
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# simulate
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if [ $SKIP_SIM -eq 0 ]; then
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./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
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fi
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