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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [mega/] [in_buf.v] - Blame information for rev 222

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1 221 olivier.gi 
// megafunction wizard: %ALTIOBUF%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altiobuf_in
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// ============================================================
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// File Name: in_buf.v
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// Megafunction Name(s):
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//                      altiobuf_in
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//
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// Simulation Library Files(s):
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//                      cyclonev
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 15.0.0 Build 145 04/22/2015 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, the Altera Quartus II License Agreement,
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//the Altera MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Altera and sold by Altera or its
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//authorized distributors.  Please refer to the applicable
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//agreement for further details.
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//altiobuf_in CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" datain dataout
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//VERSION_BEGIN 15.0 cbx_altiobuf_in 2015:04:15:19:11:38:SJ cbx_mgl 2015:04:15:20:18:26:SJ cbx_stratixiii 2015:04:15:19:11:39:SJ cbx_stratixv 2015:04:15:19:11:39:SJ  VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = cyclonev_io_ibuf 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module  in_buf_iobuf_in_v0i
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        (
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        datain,
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        dataout) ;
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        input   [0:0]  datain;
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        output   [0:0]  dataout;
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        wire  [0:0]   wire_ibufa_o;
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        cyclonev_io_ibuf   ibufa_0
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        (
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        .i(datain),
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        .o(wire_ibufa_o[0:0])
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_off
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        `endif
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        ,
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        .dynamicterminationcontrol(1'b0),
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        .ibar(1'b0)
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        `ifndef FORMAL_VERIFICATION
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        // synopsys translate_on
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        `endif
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        );
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        defparam
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                ibufa_0.bus_hold = "false",
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                ibufa_0.differential_mode = "false",
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                ibufa_0.lpm_type = "cyclonev_io_ibuf";
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        assign
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                dataout = wire_ibufa_o;
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endmodule //in_buf_iobuf_in_v0i
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//VALID FILE
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module in_buf (
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        datain,
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        dataout);
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        input   [0:0]  datain;
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        output  [0:0]  dataout;
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        wire [0:0] sub_wire0;
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        wire [0:0] dataout = sub_wire0[0:0];
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        in_buf_iobuf_in_v0i     in_buf_iobuf_in_v0i_component (
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                                .datain (datain),
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                                .dataout (sub_wire0));
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
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// Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
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// Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
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// Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
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// Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
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// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
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// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
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// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL in_buf_bb.v FALSE
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// Retrieval info: LIB_FILE: cyclonev

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