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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [mega/] [ram_16x16k.v] - Blame information for rev 221

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1 221 olivier.gi
// megafunction wizard: %RAM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: ram_16x16k.v
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// Megafunction Name(s):
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//                      altsyncram
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//
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// Simulation Library Files(s):
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//                      altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 15.0.0 Build 145 04/22/2015 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, the Altera Quartus II License Agreement,
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//the Altera MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Altera and sold by Altera or its
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//authorized distributors.  Please refer to the applicable
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//agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module ram_16x16k (
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        address,
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        byteena,
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        clken,
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        clock,
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        data,
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        wren,
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        q);
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        input   [13:0]  address;
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        input   [1:0]  byteena;
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        input     clken;
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        input     clock;
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        input   [15:0]  data;
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        input     wren;
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        output  [15:0]  q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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        tri1    [1:0]  byteena;
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        tri1      clken;
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        tri1      clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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        wire [15:0] sub_wire0;
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        wire [15:0] q = sub_wire0[15:0];
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        altsyncram      altsyncram_component (
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                                .address_a (address),
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                                .byteena_a (byteena),
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                                .clock0 (clock),
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                                .clocken0 (clken),
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                                .data_a (data),
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                                .wren_a (wren),
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                                .q_a (sub_wire0),
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                                .aclr0 (1'b0),
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                                .aclr1 (1'b0),
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                                .address_b (1'b1),
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                                .addressstall_a (1'b0),
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                                .addressstall_b (1'b0),
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                                .byteena_b (1'b1),
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                                .clock1 (1'b1),
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                                .clocken1 (1'b1),
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                                .clocken2 (1'b1),
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                                .clocken3 (1'b1),
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                                .data_b (1'b1),
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                                .eccstatus (),
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                                .q_b (),
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                                .rden_a (1'b1),
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                                .rden_b (1'b1),
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                                .wren_b (1'b0));
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        defparam
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                altsyncram_component.byte_size = 8,
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                altsyncram_component.clock_enable_input_a = "NORMAL",
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                altsyncram_component.clock_enable_output_a = "BYPASS",
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                altsyncram_component.init_file = "pmem.mif",
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                altsyncram_component.intended_device_family = "Cyclone V",
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                altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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                altsyncram_component.lpm_type = "altsyncram",
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                altsyncram_component.numwords_a = 16384,
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                altsyncram_component.operation_mode = "SINGLE_PORT",
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                altsyncram_component.outdata_aclr_a = "NONE",
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                altsyncram_component.outdata_reg_a = "UNREGISTERED",
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                altsyncram_component.power_up_uninitialized = "FALSE",
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                altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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                altsyncram_component.widthad_a = 14,
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                altsyncram_component.width_a = 16,
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                altsyncram_component.width_byteena_a = 2;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrData NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "1"
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// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "pmem.ihex"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegData NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
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// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
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// Retrieval info: PRIVATE: WidthData NUMERIC "16"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "pmem.ihex"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
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// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
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// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]"
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// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
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// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
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// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
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// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x16k.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x16k.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x16k.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x16k.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x16k_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_16x16k_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf

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