URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [mega/] [ram_16x512_dp.qip] - Blame information for rev 221

Line No.	Rev	Author	Line
1	221	olivier.gi	`set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"`
2			`set_global_assignment -name IP_TOOL_VERSION "15.0"`
3			`set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"`
4			`set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_16x512_dp.v"]`