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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_de0_nano_soc_led_key_sw.v
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//
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// *Module Description:
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// Custom peripheral for the DE0 Nano SoC board
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// for driving LEDs and reading SWITCHES and KEYs (i.e. buttons)
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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module omsp_de0_nano_soc_led_key_sw (
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// OUTPUTs
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irq_key, // Key/Button interrupt
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irq_sw, // Switch interrupt
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led, // LED output control
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per_dout, // Peripheral data output
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// INPUTs
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mclk, // Main system clock
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key, // key/button inputs
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sw, // switches inputs
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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puc_rst // Main system reset
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);
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// OUTPUTs
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//=========
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output irq_key; // Key/Button interrupt
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output irq_sw; // Switch interrupt
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output [7:0] led; // LED output control
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output [15:0] per_dout; // Peripheral data output
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// INPUTs
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//=========
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input mclk; // Main system clock
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input [1:0] key; // key/button inputs
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input [3:0] sw; // switches inputs
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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//=============================================================================
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// 1) PARAMETER DECLARATION
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//=============================================================================
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// Register base address (must be aligned to decoder bit width)
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parameter [14:0] BASE_ADDR = 15'h0090;
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DEC_WD = 3;
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// Register addresses offset
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parameter [DEC_WD-1:0] LED_CTRL = 'h0,
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KEY_SW_VAL = 'h1,
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KEY_SW_IRQ_EN = 'h2,
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KEY_SW_IRQ_EDGE = 'h3,
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KEY_SW_IRQ_VAL = 'h4;
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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parameter [DEC_SZ-1:0] LED_CTRL_D = (BASE_REG << LED_CTRL ),
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KEY_SW_VAL_D = (BASE_REG << KEY_SW_VAL ),
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KEY_SW_IRQ_EN_D = (BASE_REG << KEY_SW_IRQ_EN ),
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KEY_SW_IRQ_EDGE_D = (BASE_REG << KEY_SW_IRQ_EDGE),
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KEY_SW_IRQ_VAL_D = (BASE_REG << KEY_SW_IRQ_VAL );
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//============================================================================
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// 2) REGISTER DECODER
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//============================================================================
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
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// Register address decode
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wire [DEC_SZ-1:0] reg_dec = (LED_CTRL_D & {DEC_SZ{(reg_addr==(LED_CTRL >>1))}}) |
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(KEY_SW_VAL_D & {DEC_SZ{(reg_addr==(KEY_SW_VAL >>1))}}) |
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(KEY_SW_IRQ_EN_D & {DEC_SZ{(reg_addr==(KEY_SW_IRQ_EN >>1))}}) |
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(KEY_SW_IRQ_EDGE_D & {DEC_SZ{(reg_addr==(KEY_SW_IRQ_EDGE >>1))}}) |
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(KEY_SW_IRQ_VAL_D & {DEC_SZ{(reg_addr==(KEY_SW_IRQ_VAL >>1))}});
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// Read/Write probes
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wire reg_lo_write = per_we[0] & reg_sel;
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wire reg_hi_write = per_we[1] & reg_sel;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
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wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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// 3) REGISTERS
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//============================================================================
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// LED Control Register
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//----------------------
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reg [7:0] led_ctrl;
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wire led_ctrl_wr = LED_CTRL[0] ? reg_hi_wr[LED_CTRL] : reg_lo_wr[LED_CTRL];
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wire [7:0] led_ctrl_nxt = LED_CTRL[0] ? per_din[15:8] : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) led_ctrl <= 8'h00;
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else if (led_ctrl_wr) led_ctrl <= led_ctrl_nxt;
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assign led = led_ctrl;
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// KEY_SW_VAL Register
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//---------------------
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// Synchronize and debounce the input signals
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wire [1:0] key_deb;
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wire [3:0] sw_deb;
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sync_debouncer_10ms sync_debouncer_10ms_key1 (.signal_debounced(key_deb[1]), .clk_50mhz(mclk), .rst(puc_rst), .signal_async(key[1]));
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sync_debouncer_10ms sync_debouncer_10ms_key0 (.signal_debounced(key_deb[0]), .clk_50mhz(mclk), .rst(puc_rst), .signal_async(key[0]));
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sync_debouncer_10ms sync_debouncer_10ms_sw3 (.signal_debounced(sw_deb[3]), .clk_50mhz(mclk), .rst(puc_rst), .signal_async(sw[3]));
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sync_debouncer_10ms sync_debouncer_10ms_sw2 (.signal_debounced(sw_deb[2]), .clk_50mhz(mclk), .rst(puc_rst), .signal_async(sw[2]));
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sync_debouncer_10ms sync_debouncer_10ms_sw1 (.signal_debounced(sw_deb[1]), .clk_50mhz(mclk), .rst(puc_rst), .signal_async(sw[1]));
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sync_debouncer_10ms sync_debouncer_10ms_sw0 (.signal_debounced(sw_deb[0]), .clk_50mhz(mclk), .rst(puc_rst), .signal_async(sw[0]));
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wire [7:0] key_sw_val = {1'b0, 1'b0, key_deb[1], key_deb[0],
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sw_deb[3], sw_deb[2], sw_deb[1], sw_deb[0] };
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// KEY_SW_IRQ_EN Register
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//----------------------
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reg [7:0] key_sw_irq_en;
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wire key_sw_irq_en_wr = KEY_SW_IRQ_EN[0] ? reg_hi_wr[KEY_SW_IRQ_EN] : reg_lo_wr[KEY_SW_IRQ_EN];
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wire [7:0] key_sw_irq_en_nxt = KEY_SW_IRQ_EN[0] ? per_din[15:8] : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) key_sw_irq_en <= 8'h00;
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else if (key_sw_irq_en_wr) key_sw_irq_en <= key_sw_irq_en_nxt & 8'h3F;
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// KEY_SW_IRQ_EDGE Register
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//--------------------------
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reg [7:0] key_sw_irq_edge;
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wire key_sw_irq_edge_wr = KEY_SW_IRQ_EDGE[0] ? reg_hi_wr[KEY_SW_IRQ_EDGE] : reg_lo_wr[KEY_SW_IRQ_EDGE];
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wire [7:0] key_sw_irq_edge_nxt = KEY_SW_IRQ_EDGE[0] ? per_din[15:8] : per_din[7:0];
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) key_sw_irq_edge <= 8'h00;
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else if (key_sw_irq_edge_wr) key_sw_irq_edge <= key_sw_irq_edge_nxt & 8'h3F;
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// KEY_SW_IRQ_VAL Register
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//-------------------------
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reg [7:0] key_sw_irq_val;
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wire key_sw_irq_val_wr = KEY_SW_IRQ_VAL[0] ? reg_hi_wr[KEY_SW_IRQ_VAL] : reg_lo_wr[KEY_SW_IRQ_VAL];
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wire [7:0] key_sw_irq_val_nxt = KEY_SW_IRQ_VAL[0] ? per_din[15:8] : per_din[7:0];
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wire [5:0] key_sw_irq_clr = key_sw_irq_val_nxt[5:0] & {6{key_sw_irq_val_wr}}; // Clear IRQ flag when 1 is writen
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wire [5:0] key_sw_irq_set;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) key_sw_irq_val <= 8'h00;
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else key_sw_irq_val <= {2'b00, (key_sw_irq_set | (~key_sw_irq_clr & key_sw_irq_val[5:0]))}; // IRQ set has priority over clear
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assign irq_key = |key_sw_irq_val[5:4];
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assign irq_sw = |key_sw_irq_val[3:0];
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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// Data output mux
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wire [15:0] led_ctrl_rd = (led_ctrl & {8{reg_rd[LED_CTRL]}}) << (8 & {4{LED_CTRL[0]}});
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wire [15:0] key_sw_val_rd = (key_sw_val & {8{reg_rd[KEY_SW_VAL]}}) << (8 & {4{KEY_SW_VAL[0]}});
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wire [15:0] key_sw_irq_en_rd = (key_sw_irq_en & {8{reg_rd[KEY_SW_IRQ_EN]}}) << (8 & {4{KEY_SW_IRQ_EN[0]}});
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wire [15:0] key_sw_irq_edge_rd = (key_sw_irq_edge & {8{reg_rd[KEY_SW_IRQ_EDGE]}}) << (8 & {4{KEY_SW_IRQ_EDGE[0]}});
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wire [15:0] key_sw_irq_val_rd = (key_sw_irq_val & {8{reg_rd[KEY_SW_IRQ_VAL]}}) << (8 & {4{KEY_SW_IRQ_VAL[0]}});
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wire [15:0] per_dout = led_ctrl_rd |
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key_sw_val_rd |
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key_sw_irq_en_rd |
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key_sw_irq_edge_rd |
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key_sw_irq_val_rd;
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//============================================================================
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// 5) IRQ GENERATION
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//============================================================================
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// Delay debounced signal for edge detection
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reg [5:0] key_sw_deb_dly;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) key_sw_deb_dly <= 6'h00;
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else key_sw_deb_dly <= key_sw_val[5:0];
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wire [5:0] key_sw_posedge = ~key_sw_val[5:0] & key_sw_deb_dly;
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wire [5:0] key_sw_negedge = key_sw_val[5:0] & ~key_sw_deb_dly;
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wire [5:0] key_sw_edge = (key_sw_posedge & key_sw_irq_edge[5:0]) |
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(key_sw_negedge & ~key_sw_irq_edge[5:0]);
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assign key_sw_irq_set = key_sw_irq_en[5:0] & key_sw_edge;
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endmodule // omsp_de0_nano_soc_led_key_sw
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