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//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_backend_lut_fifo.v
//
// *Module Description:
//                      Mini-cache memory for the LUT memory accesses.
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
 
module  ogfx_backend_lut_fifo (
 
// OUTPUTs
    frame_data_request_o,                        // Request for next frame data
 
    refresh_data_o,                              // Display Refresh data
    refresh_data_ready_o,                        // Display Refresh data ready
 
`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_addr_o,                              // LUT-RAM address
    lut_ram_cen_o,                               // LUT-RAM enable (active low)
`endif
 
// INPUTs
    mclk,                                        // Main system clock
    puc_rst,                                     // Main system reset
 
    frame_data_i,                                // Frame data
    frame_data_ready_i,                          // Frame data ready
 
    gfx_mode_i,                                  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
 
`ifdef WITH_PROGRAMMABLE_LUT
    lut_ram_dout_i,                              // LUT-RAM data output
    lut_ram_dout_rdy_nxt_i,                      // LUT-RAM data output ready during next cycle
`endif
 
    refresh_active_i,                            // Display refresh on going
    refresh_data_request_i,                      // Request for next refresh data
    refresh_lut_select_i                         // Refresh LUT bank selection
);
 
// OUTPUTs
//=========
output               frame_data_request_o;       // Request for next frame data
 
output        [15:0] refresh_data_o;             // Display Refresh data
output               refresh_data_ready_o;       // Display Refresh data ready
 
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o;             // LUT-RAM address
output               lut_ram_cen_o;              // LUT-RAM enable (active low)
`endif
 
// INPUTs
//=========
input                mclk;                       // Main system clock
input                puc_rst;                    // Main system reset
 
input         [15:0] frame_data_i;               // Frame data
input                frame_data_ready_i;         // Frame data ready
 
input          [2:0] gfx_mode_i;                 // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
 
`ifdef WITH_PROGRAMMABLE_LUT
input         [15:0] lut_ram_dout_i;             // LUT-RAM data output
input                lut_ram_dout_rdy_nxt_i;     // LUT-RAM data output ready during next cycle
`endif
 
input                refresh_active_i;           // Display refresh on going
input                refresh_data_request_i;     // Request for next refresh data
input          [1:0] refresh_lut_select_i;       // Refresh LUT bank selection
 
 
//=============================================================================
// 1)  WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
 
// State machine registers
reg    [1:0] lut_state;
reg    [1:0] lut_state_nxt;
 
// State definition
parameter    STATE_IDLE        =   0,
             STATE_FRAME_DATA  =   1,
             STATE_LUT_DATA    =   2,
             STATE_HOLD        =   3;
 
// Some parameter(s)
parameter    FIFO_EMPTY        =  3'h0,
             FIFO_FULL         =  3'h5;
 
// Video modes decoding
wire         gfx_mode_1_bpp    =  (gfx_mode_i == 3'b000);
wire         gfx_mode_2_bpp    =  (gfx_mode_i == 3'b001);
wire         gfx_mode_4_bpp    =  (gfx_mode_i == 3'b010);
wire         gfx_mode_8_bpp    =  (gfx_mode_i == 3'b011);
wire         gfx_mode_16_bpp   = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
                                   gfx_mode_2_bpp | gfx_mode_1_bpp);
 
// Others
reg    [2:0] fifo_counter;
wire   [2:0] fifo_counter_nxt;
 
 
//============================================================================
// 2) HARD CODED LOOKUP TABLE
//============================================================================
 
wire  [15:0] lut_hw_data_1_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[0]  ==1'b0   }}) |                            // 1 bpp:  Black
                                 ({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[0]  ==1'b1   }}) ;                            //         White
 
wire  [15:0] lut_hw_data_2_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[1:0]==2'b00  }}) |                            // 2 bpp:  Black
                                 ({5'b01000, 6'b010000, 5'b01000} & {16{frame_data_i[1:0]==2'b01  }}) |                            //         Dark Gray
                                 ({5'b11000, 6'b110000, 5'b11000} & {16{frame_data_i[1:0]==2'b10  }}) |                            //         Light Gray
                                 ({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[1:0]==2'b11  }}) ;                            //         White
 
wire  [15:0] lut_hw_data_4_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0000}}) |                            // 4 bpp:  Black
                                 ({5'b00000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0001}}) |                            //         Dark Blue
                                 ({5'b10000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0010}}) |                            //         Dark Red
                                 ({5'b10000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0011}}) |                            //         Dark Magenta
                                 ({5'b00000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0100}}) |                            //         Dark Green
                                 ({5'b00000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0101}}) |                            //         Dark Cyan
                                 ({5'b10000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0110}}) |                            //         Dark Yellow
                                 ({5'b10000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0111}}) |                            //         Gray
                                 ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1000}}) |                            //         Black
                                 ({5'b00000, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1001}}) |                            //         Blue
                                 ({5'b11111, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1010}}) |                            //         Red
                                 ({5'b11111, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1011}}) |                            //         Magenta
                                 ({5'b00000, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1100}}) |                            //         Green
                                 ({5'b00000, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1101}}) |                            //         Cyan
                                 ({5'b11111, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1110}}) |                            //         Yellow
                                 ({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1111}});                             //         White
 
wire  [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5],                 // 8 bpp:  R = D<7,6,5,5,5>
                                  frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], //         G = D<4,3,2,2,2,2>
                                  frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]};                //         B = D<1,0,0,0,0>
 
wire  [15:0] lut_hw_data       = (lut_hw_data_1_bpp & {16{gfx_mode_1_bpp}}) |
                                 (lut_hw_data_2_bpp & {16{gfx_mode_2_bpp}}) |
                                 (lut_hw_data_4_bpp & {16{gfx_mode_4_bpp}}) |
                                 (lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
 
wire         lut_hw_enabled    = ~gfx_mode_16_bpp   & ~refresh_lut_select_i[0];
wire         lut_sw_enabled    = ~gfx_mode_16_bpp   &  refresh_lut_select_i[0];
 
 
//============================================================================
// 3) STATE MACHINE
//============================================================================
 
//--------------------------------
// States Transitions
//--------------------------------
always @(lut_state or refresh_active_i or frame_data_ready_i     or
`ifdef WITH_PROGRAMMABLE_LUT
                      lut_sw_enabled   or lut_ram_dout_rdy_nxt_i or
`endif
                      fifo_counter_nxt)
    case(lut_state)
 
      STATE_IDLE           :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       : STATE_FRAME_DATA ;
 
      STATE_FRAME_DATA     :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                              ~frame_data_ready_i           ? STATE_FRAME_DATA :
`ifdef WITH_PROGRAMMABLE_LUT
                                               lut_sw_enabled               ? STATE_LUT_DATA   :
`endif
                                                                                                 STATE_HOLD       ;
 
`ifdef WITH_PROGRAMMABLE_LUT
      STATE_LUT_DATA       :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                               lut_ram_dout_rdy_nxt_i       ? STATE_HOLD       : STATE_LUT_DATA   ;
`endif
 
      STATE_HOLD           :  lut_state_nxt = ~refresh_active_i             ? STATE_IDLE       :
                                              (fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD       ;
 
    // pragma coverage off
      default              :  lut_state_nxt =  STATE_IDLE;
    // pragma coverage on
    endcase
 
//--------------------------------
// State machine
//--------------------------------
always @(posedge mclk or posedge puc_rst)
  if (puc_rst) lut_state  <= STATE_IDLE;
  else         lut_state  <= lut_state_nxt;
 
 
// Request for the next frame data
assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);
 
 
//============================================================================
// 4) LUT MEMORY INTERFACE
//============================================================================
 
//--------------------------------
// Enable
//--------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
   assign lut_ram_cen_o  = ~(lut_state == STATE_LUT_DATA);
`endif
 
//--------------------------------
// Address
//--------------------------------
// Mask with chip enable to save power
 
`ifdef WITH_PROGRAMMABLE_LUT
  `ifdef WITH_EXTRA_LUT_BANK
    // Allow LUT bank switching only when the refresh is not on going
    reg refresh_lut_bank_select_sync;
    always @(posedge mclk or posedge puc_rst)
      if (puc_rst)                refresh_lut_bank_select_sync  <=  1'b0;
      else if (~refresh_active_i) refresh_lut_bank_select_sync  <=  refresh_lut_select_i[1];
 
    assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
  `else
    assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
  `endif
`endif
 
//--------------------------------
// Data Ready
//--------------------------------
// When filling the FIFO, the data is available on the bus
// one cycle after the rdy_nxt signal
reg            lut_ram_dout_ready;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst) lut_ram_dout_ready  <=  1'b0;
`ifdef WITH_PROGRAMMABLE_LUT
  else         lut_ram_dout_ready  <=  lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
                                                        (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`else
  else         lut_ram_dout_ready  <=  (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`endif
 
 
//============================================================================
// 5) FIFO COUNTER
//============================================================================
 
// Control signals
wire      fifo_push =  lut_ram_dout_ready     & (fifo_counter != FIFO_FULL);
wire      fifo_pop  =  refresh_data_request_i & (fifo_counter != FIFO_EMPTY);
 
// Fifo counter
assign fifo_counter_nxt = ~refresh_active_i      ?  FIFO_EMPTY          : // Initialize
                          (fifo_push & fifo_pop) ?  fifo_counter        : // Keep value (pop & push at the same time)
                           fifo_push             ?  fifo_counter + 3'h1 : // Push
                           fifo_pop              ?  fifo_counter - 3'h1 : // Pop
                                                    fifo_counter;         // Hold
 
always @(posedge mclk or posedge puc_rst)
  if (puc_rst) fifo_counter <= FIFO_EMPTY;
  else         fifo_counter <= fifo_counter_nxt;
 
 
//============================================================================
// 6) FIFO MEMORY & RD/WR POINTERS
//============================================================================
 
// Write pointer
reg [2:0] wr_ptr;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                    wr_ptr  <=  3'h0;
  else if (~refresh_active_i)     wr_ptr  <=  3'h0;
  else if (fifo_push)
    begin
       if (wr_ptr==(FIFO_FULL-1)) wr_ptr  <=  3'h0;
       else                       wr_ptr  <=  wr_ptr + 3'h1;
    end
 
// Memory
reg [15:0] fifo_mem [0:4];
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)
    begin
       fifo_mem[0]      <=  16'h0000;
       fifo_mem[1]      <=  16'h0000;
       fifo_mem[2]      <=  16'h0000;
       fifo_mem[3]      <=  16'h0000;
       fifo_mem[4]      <=  16'h0000;
    end
  else if (fifo_push)
    begin
       fifo_mem[wr_ptr] <=  lut_hw_enabled ? lut_hw_data    :
`ifdef WITH_PROGRAMMABLE_LUT
                            lut_sw_enabled ? lut_ram_dout_i :
`endif
                                             frame_data_i;
    end
 
// Read pointer
reg [2:0] rd_ptr;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                    rd_ptr  <=  3'h0;
  else if (~refresh_active_i)     rd_ptr  <=  3'h0;
  else if (fifo_pop)
    begin
       if (rd_ptr==(FIFO_FULL-1)) rd_ptr  <=  3'h0;
       else                       rd_ptr  <=  rd_ptr + 3'h1;
    end
 
//============================================================================
// 7) REFRESH_DATA
//============================================================================
 
// Refresh Data is ready
reg        refresh_data_ready_o;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                refresh_data_ready_o <=  1'h0;
  else if (~refresh_active_i) refresh_data_ready_o <=  1'h0;
  else                        refresh_data_ready_o <=  fifo_pop;
 
// Refresh Data
reg [15:0] refresh_data_o;
always @(posedge mclk or posedge puc_rst)
  if (puc_rst)                refresh_data_o <= 16'h0000;
  else if (fifo_pop)          refresh_data_o <= fifo_mem[rd_ptr];
 
 
endmodule // ogfx_backend_lut_fifo
 
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif

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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [opengfx430/] [ogfx_backend_lut_fifo.v] - Blame information for rev 221

Line No.	Rev	Author	Line
1	221	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2015 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: ogfx_backend_lut_fifo.v`
26			`//`
27			`// *Module Description:`
28			`// Mini-cache memory for the LUT memory accesses.`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34			`// $Rev$`
35			`// $LastChangedBy$`
36			`// $LastChangedDate$`
37			`//----------------------------------------------------------------------------`
38			`ifdef OGFX_NO_INCLUDE
39			`else
40			`include "openGFX430_defines.v"
41			`endif
42
43			`module ogfx_backend_lut_fifo (`
44
45			`// OUTPUTs`
46			`frame_data_request_o, // Request for next frame data`
47
48			`refresh_data_o, // Display Refresh data`
49			`refresh_data_ready_o, // Display Refresh data ready`
50
51			`ifdef WITH_PROGRAMMABLE_LUT
52			`lut_ram_addr_o, // LUT-RAM address`
53			`lut_ram_cen_o, // LUT-RAM enable (active low)`
54			`endif
55
56			`// INPUTs`
57			`mclk, // Main system clock`
58			`puc_rst, // Main system reset`
59
60			`frame_data_i, // Frame data`
61			`frame_data_ready_i, // Frame data ready`
62
63			`gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)`
64
65			`ifdef WITH_PROGRAMMABLE_LUT
66			`lut_ram_dout_i, // LUT-RAM data output`
67			`lut_ram_dout_rdy_nxt_i, // LUT-RAM data output ready during next cycle`
68			`endif
69
70			`refresh_active_i, // Display refresh on going`
71			`refresh_data_request_i, // Request for next refresh data`
72			`refresh_lut_select_i // Refresh LUT bank selection`
73			`);`
74
75			`// OUTPUTs`
76			`//=========`
77			`output frame_data_request_o; // Request for next frame data`
78
79			`output [15:0] refresh_data_o; // Display Refresh data`
80			`output refresh_data_ready_o; // Display Refresh data ready`
81
82			`ifdef WITH_PROGRAMMABLE_LUT
83			output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
84			`output lut_ram_cen_o; // LUT-RAM enable (active low)`
85			`endif
86
87			`// INPUTs`
88			`//=========`
89			`input mclk; // Main system clock`
90			`input puc_rst; // Main system reset`
91
92			`input [15:0] frame_data_i; // Frame data`
93			`input frame_data_ready_i; // Frame data ready`
94
95			`input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)`
96
97			`ifdef WITH_PROGRAMMABLE_LUT
98			`input [15:0] lut_ram_dout_i; // LUT-RAM data output`
99			`input lut_ram_dout_rdy_nxt_i; // LUT-RAM data output ready during next cycle`
100			`endif
101
102			`input refresh_active_i; // Display refresh on going`
103			`input refresh_data_request_i; // Request for next refresh data`
104			`input [1:0] refresh_lut_select_i; // Refresh LUT bank selection`
105
106
107			`//=============================================================================`
108			`// 1) WIRE, REGISTERS AND PARAMETER DECLARATION`
109			`//=============================================================================`
110
111			`// State machine registers`
112			`reg [1:0] lut_state;`
113			`reg [1:0] lut_state_nxt;`
114
115			`// State definition`
116			`parameter STATE_IDLE = 0,`
117			`STATE_FRAME_DATA = 1,`
118			`STATE_LUT_DATA = 2,`
119			`STATE_HOLD = 3;`
120
121			`// Some parameter(s)`
122			`parameter FIFO_EMPTY = 3'h0,`
123			`FIFO_FULL = 3'h5;`
124
125			`// Video modes decoding`
126			`wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);`
127			`wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);`
128			`wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);`
129			`wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);`
130			`wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp \| gfx_mode_4_bpp \|`
131			`gfx_mode_2_bpp \| gfx_mode_1_bpp);`
132
133			`// Others`
134			`reg [2:0] fifo_counter;`
135			`wire [2:0] fifo_counter_nxt;`
136
137
138			`//============================================================================`
139			`// 2) HARD CODED LOOKUP TABLE`
140			`//============================================================================`
141
142			`wire [15:0] lut_hw_data_1_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[0] ==1'b0 }}) \| // 1 bpp: Black`
143			`({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[0] ==1'b1 }}) ; // White`
144
145			`wire [15:0] lut_hw_data_2_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[1:0]==2'b00 }}) \| // 2 bpp: Black`
146			`({5'b01000, 6'b010000, 5'b01000} & {16{frame_data_i[1:0]==2'b01 }}) \| // Dark Gray`
147			`({5'b11000, 6'b110000, 5'b11000} & {16{frame_data_i[1:0]==2'b10 }}) \| // Light Gray`
148			`({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[1:0]==2'b11 }}) ; // White`
149
150			`wire [15:0] lut_hw_data_4_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0000}}) \| // 4 bpp: Black`
151			`({5'b00000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0001}}) \| // Dark Blue`
152			`({5'b10000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0010}}) \| // Dark Red`
153			`({5'b10000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0011}}) \| // Dark Magenta`
154			`({5'b00000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0100}}) \| // Dark Green`
155			`({5'b00000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0101}}) \| // Dark Cyan`
156			`({5'b10000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0110}}) \| // Dark Yellow`
157			`({5'b10000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0111}}) \| // Gray`
158			`({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1000}}) \| // Black`
159			`({5'b00000, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1001}}) \| // Blue`
160			`({5'b11111, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1010}}) \| // Red`
161			`({5'b11111, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1011}}) \| // Magenta`
162			`({5'b00000, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1100}}) \| // Green`
163			`({5'b00000, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1101}}) \| // Cyan`
164			`({5'b11111, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1110}}) \| // Yellow`
165			`({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1111}}); // White`
166
167			`wire [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5], // 8 bpp: R = D<7,6,5,5,5>`
168			`frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], // G = D<4,3,2,2,2,2>`
169			`frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]}; // B = D<1,0,0,0,0>`
170
171			`wire [15:0] lut_hw_data = (lut_hw_data_1_bpp & {16{gfx_mode_1_bpp}}) \|`
172			`(lut_hw_data_2_bpp & {16{gfx_mode_2_bpp}}) \|`
173			`(lut_hw_data_4_bpp & {16{gfx_mode_4_bpp}}) \|`
174			`(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});`
175
176			`wire lut_hw_enabled = ~gfx_mode_16_bpp & ~refresh_lut_select_i[0];`
177			`wire lut_sw_enabled = ~gfx_mode_16_bpp & refresh_lut_select_i[0];`
178
179
180			`//============================================================================`
181			`// 3) STATE MACHINE`
182			`//============================================================================`
183
184			`//--------------------------------`
185			`// States Transitions`
186			`//--------------------------------`
187			`always @(lut_state or refresh_active_i or frame_data_ready_i or`
188			`ifdef WITH_PROGRAMMABLE_LUT
189			`lut_sw_enabled or lut_ram_dout_rdy_nxt_i or`
190			`endif
191			`fifo_counter_nxt)`
192			`case(lut_state)`
193
194			`STATE_IDLE : lut_state_nxt = ~refresh_active_i ? STATE_IDLE : STATE_FRAME_DATA ;`
195
196			`STATE_FRAME_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :`
197			`~frame_data_ready_i ? STATE_FRAME_DATA :`
198			`ifdef WITH_PROGRAMMABLE_LUT
199			`lut_sw_enabled ? STATE_LUT_DATA :`
200			`endif
201			`STATE_HOLD ;`
202
203			`ifdef WITH_PROGRAMMABLE_LUT
204			`STATE_LUT_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :`
205			`lut_ram_dout_rdy_nxt_i ? STATE_HOLD : STATE_LUT_DATA ;`
206			`endif
207
208			`STATE_HOLD : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :`
209			`(fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD ;`
210
211			`// pragma coverage off`
212			`default : lut_state_nxt = STATE_IDLE;`
213			`// pragma coverage on`
214			`endcase`
215
216			`//--------------------------------`
217			`// State machine`
218			`//--------------------------------`
219			`always @(posedge mclk or posedge puc_rst)`
220			`if (puc_rst) lut_state <= STATE_IDLE;`
221			`else lut_state <= lut_state_nxt;`
222
223
224			`// Request for the next frame data`
225			`assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);`
226
227
228			`//============================================================================`
229			`// 4) LUT MEMORY INTERFACE`
230			`//============================================================================`
231
232			`//--------------------------------`
233			`// Enable`
234			`//--------------------------------`
235			`ifdef WITH_PROGRAMMABLE_LUT
236			`assign lut_ram_cen_o = ~(lut_state == STATE_LUT_DATA);`
237			`endif
238
239			`//--------------------------------`
240			`// Address`
241			`//--------------------------------`
242			`// Mask with chip enable to save power`
243
244			`ifdef WITH_PROGRAMMABLE_LUT
245			`ifdef WITH_EXTRA_LUT_BANK
246			`// Allow LUT bank switching only when the refresh is not on going`
247			`reg refresh_lut_bank_select_sync;`
248			`always @(posedge mclk or posedge puc_rst)`
249			`if (puc_rst) refresh_lut_bank_select_sync <= 1'b0;`
250			`else if (~refresh_active_i) refresh_lut_bank_select_sync <= refresh_lut_select_i[1];`
251
252			`assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};`
253			`else
254			`assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};`
255			`endif
256			`endif
257
258			`//--------------------------------`
259			`// Data Ready`
260			`//--------------------------------`
261			`// When filling the FIFO, the data is available on the bus`
262			`// one cycle after the rdy_nxt signal`
263			`reg lut_ram_dout_ready;`
264			`always @(posedge mclk or posedge puc_rst)`
265			`if (puc_rst) lut_ram_dout_ready <= 1'b0;`
266			`ifdef WITH_PROGRAMMABLE_LUT
267			`else lut_ram_dout_ready <= lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :`
268			`(frame_data_ready_i & (lut_state == STATE_FRAME_DATA));`
269			`else
270			`else lut_ram_dout_ready <= (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));`
271			`endif
272
273
274			`//============================================================================`
275			`// 5) FIFO COUNTER`
276			`//============================================================================`
277
278			`// Control signals`
279			`wire fifo_push = lut_ram_dout_ready & (fifo_counter != FIFO_FULL);`
280			`wire fifo_pop = refresh_data_request_i & (fifo_counter != FIFO_EMPTY);`
281
282			`// Fifo counter`
283			`assign fifo_counter_nxt = ~refresh_active_i ? FIFO_EMPTY : // Initialize`
284			`(fifo_push & fifo_pop) ? fifo_counter : // Keep value (pop & push at the same time)`
285			`fifo_push ? fifo_counter + 3'h1 : // Push`
286			`fifo_pop ? fifo_counter - 3'h1 : // Pop`
287			`fifo_counter; // Hold`
288
289			`always @(posedge mclk or posedge puc_rst)`
290			`if (puc_rst) fifo_counter <= FIFO_EMPTY;`
291			`else fifo_counter <= fifo_counter_nxt;`
292
293
294			`//============================================================================`
295			`// 6) FIFO MEMORY & RD/WR POINTERS`
296			`//============================================================================`
297
298			`// Write pointer`
299			`reg [2:0] wr_ptr;`
300			`always @(posedge mclk or posedge puc_rst)`
301			`if (puc_rst) wr_ptr <= 3'h0;`
302			`else if (~refresh_active_i) wr_ptr <= 3'h0;`
303			`else if (fifo_push)`
304			`begin`
305			`if (wr_ptr==(FIFO_FULL-1)) wr_ptr <= 3'h0;`
306			`else wr_ptr <= wr_ptr + 3'h1;`
307			`end`
308
309			`// Memory`
310			`reg [15:0] fifo_mem [0:4];`
311			`always @(posedge mclk or posedge puc_rst)`
312			`if (puc_rst)`
313			`begin`
314			`fifo_mem[0] <= 16'h0000;`
315			`fifo_mem[1] <= 16'h0000;`
316			`fifo_mem[2] <= 16'h0000;`
317			`fifo_mem[3] <= 16'h0000;`
318			`fifo_mem[4] <= 16'h0000;`
319			`end`
320			`else if (fifo_push)`
321			`begin`
322			`fifo_mem[wr_ptr] <= lut_hw_enabled ? lut_hw_data :`
323			`ifdef WITH_PROGRAMMABLE_LUT
324			`lut_sw_enabled ? lut_ram_dout_i :`
325			`endif
326			`frame_data_i;`
327			`end`
328
329			`// Read pointer`
330			`reg [2:0] rd_ptr;`
331			`always @(posedge mclk or posedge puc_rst)`
332			`if (puc_rst) rd_ptr <= 3'h0;`
333			`else if (~refresh_active_i) rd_ptr <= 3'h0;`
334			`else if (fifo_pop)`
335			`begin`
336			`if (rd_ptr==(FIFO_FULL-1)) rd_ptr <= 3'h0;`
337			`else rd_ptr <= rd_ptr + 3'h1;`
338			`end`
339
340			`//============================================================================`
341			`// 7) REFRESH_DATA`
342			`//============================================================================`
343
344			`// Refresh Data is ready`
345			`reg refresh_data_ready_o;`
346			`always @(posedge mclk or posedge puc_rst)`
347			`if (puc_rst) refresh_data_ready_o <= 1'h0;`
348			`else if (~refresh_active_i) refresh_data_ready_o <= 1'h0;`
349			`else refresh_data_ready_o <= fifo_pop;`
350
351			`// Refresh Data`
352			`reg [15:0] refresh_data_o;`
353			`always @(posedge mclk or posedge puc_rst)`
354			`if (puc_rst) refresh_data_o <= 16'h0000;`
355			`else if (fifo_pop) refresh_data_o <= fifo_mem[rd_ptr];`
356
357
358			`endmodule // ogfx_backend_lut_fifo`
359
360			`ifdef OGFX_NO_INCLUDE
361			`else
362			`include "openGFX430_undefines.v"
363			`endif