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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [opengfx430/] [ogfx_gpu.v] - Blame information for rev 221

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1 221 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ogfx_gpu.v
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//
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// *Module Description:
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//                      Graphic-Processing unit of the graphic controller.
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//                      This block can perform the following hardware
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//                      accelerations:
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//
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//                          -
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//                          -
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module  ogfx_gpu (
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// OUTPUTs
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    gpu_cmd_done_evt_o,                           // GPU command done event
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    gpu_cmd_error_evt_o,                          // GPU command error event
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    gpu_dma_busy_o,                               // GPU DMA execution on going
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    gpu_get_data_o,                               // GPU get next data
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    vid_ram_addr_o,                               // Video-RAM address
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    vid_ram_din_o,                                // Video-RAM data
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    vid_ram_wen_o,                                // Video-RAM write strobe (active low)
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    vid_ram_cen_o,                                // Video-RAM chip enable (active low)
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// INPUTs
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    mclk,                                         // Main system clock
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    puc_rst,                                      // Main system reset
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    display_width_i,                              // Display width
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    gfx_mode_i,                                   // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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    gpu_data_i,                                   // GPU data
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    gpu_data_avail_i,                             // GPU data available
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    gpu_enable_i,                                 // GPU enable
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    vid_ram_dout_i,                               // Video-RAM data input
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    vid_ram_dout_rdy_nxt_i                        // Video-RAM data output ready during next cycle
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);
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// OUTPUTs
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//=========
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output               gpu_cmd_done_evt_o;          // GPU command done event
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output               gpu_cmd_error_evt_o;         // GPU command error event
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output               gpu_dma_busy_o;              // GPU DMA execution on going
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output               gpu_get_data_o;              // GPU get next data
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output [`VRAM_MSB:0] vid_ram_addr_o;              // Video-RAM address
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output        [15:0] vid_ram_din_o;               // Video-RAM data
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output               vid_ram_wen_o;               // Video-RAM write strobe (active low)
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output               vid_ram_cen_o;               // Video-RAM chip enable (active low)
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// INPUTs
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//=========
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input                mclk;                        // Main system clock
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input                puc_rst;                     // Main system reset
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input  [`LPIX_MSB:0] display_width_i;             // Display width
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input          [2:0] gfx_mode_i;                  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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input         [15:0] gpu_data_i;                  // GPU data
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input                gpu_data_avail_i;            // GPU data available
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input                gpu_enable_i;                // GPU enable
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input         [15:0] vid_ram_dout_i;              // Video-RAM data input
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input                vid_ram_dout_rdy_nxt_i;      // Video-RAM data output ready during next cycle
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//=============================================================================
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// 1)  WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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wire                 exec_fill;
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wire                 exec_copy;
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wire                 exec_copy_trans;
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wire                 trig_exec;
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wire   [`APIX_MSB:0] cfg_dst_px_addr;
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wire                 cfg_dst_cl_swp;
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wire                 cfg_dst_x_swp;
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wire                 cfg_dst_y_swp;
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wire          [15:0] cfg_fill_color;
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wire           [3:0] cfg_pix_op_sel;
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wire   [`LPIX_MSB:0] cfg_rec_width;
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wire   [`LPIX_MSB:0] cfg_rec_height;
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wire   [`APIX_MSB:0] cfg_src_px_addr;
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wire                 cfg_src_cl_swp;
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wire                 cfg_src_x_swp;
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wire                 cfg_src_y_swp;
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wire          [15:0] cfg_transparent_color;
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wire                 gpu_exec_done;
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//=============================================================================
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// 2)  GPU CONGIGURATION & CONTROL REGISTERS
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//=============================================================================
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ogfx_gpu_reg ogfx_gpu_reg_inst (
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// OUTPUTs
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    .gpu_cmd_done_evt_o      (gpu_cmd_done_evt_o    ),     // GPU command done event
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    .gpu_cmd_error_evt_o     (gpu_cmd_error_evt_o   ),     // GPU command error event
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    .gpu_get_data_o          (gpu_get_data_o        ),     // GPU get next data
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    .exec_fill_o             (exec_fill             ),     // Rectangle fill on going
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    .exec_copy_o             (exec_copy             ),     // Rectangle copy on going
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    .exec_copy_trans_o       (exec_copy_trans       ),     // Rectangle transparent copy on going
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    .trig_exec_o             (trig_exec             ),     // Trigger rectangle execution
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    .cfg_dst_px_addr_o       (cfg_dst_px_addr       ),     // Destination pixel address configuration
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    .cfg_dst_cl_swp_o        (cfg_dst_cl_swp        ),     // Destination Column/Line-Swap configuration
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    .cfg_dst_x_swp_o         (cfg_dst_x_swp         ),     // Destination X-Swap configuration
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    .cfg_dst_y_swp_o         (cfg_dst_y_swp         ),     // Destination Y-Swap configuration
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    .cfg_fill_color_o        (cfg_fill_color        ),     // Fill color (for rectangle fill operation)
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    .cfg_pix_op_sel_o        (cfg_pix_op_sel        ),     // Pixel operation to be performed during the copy
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    .cfg_rec_width_o         (cfg_rec_width         ),     // Rectangle width configuration
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    .cfg_rec_height_o        (cfg_rec_height        ),     // Rectangle height configuration
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    .cfg_src_px_addr_o       (cfg_src_px_addr       ),     // Source pixel address configuration
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    .cfg_src_cl_swp_o        (cfg_src_cl_swp        ),     // Source Column/Line-Swap configuration
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    .cfg_src_x_swp_o         (cfg_src_x_swp         ),     // Source X-Swap configuration
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    .cfg_src_y_swp_o         (cfg_src_y_swp         ),     // Source Y-Swap configuration
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    .cfg_transparent_color_o (cfg_transparent_color ),     // Transparent color (for rectangle transparent copy operation)
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// INPUTs
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    .mclk                    (mclk                  ),     // Main system clock
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    .puc_rst                 (puc_rst               ),     // Main system reset
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    .gpu_data_i              (gpu_data_i            ),     // GPU data
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    .gpu_data_avail_i        (gpu_data_avail_i      ),     // GPU data available
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    .gfx_mode_i              (gfx_mode_i            ),     // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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    .gpu_enable_i            (gpu_enable_i          ),     // GPU enable
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    .gpu_exec_done_i         (gpu_exec_done         )      // GPU execution done
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);
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//=============================================================================
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// 3)  2D-DMA
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//=============================================================================
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ogfx_gpu_dma ogfx_gpu_dma_inst (
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// OUTPUTs
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    .gpu_exec_done_o         (gpu_exec_done         ),     // GPU execution done
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    .gpu_dma_busy_o          (gpu_dma_busy_o        ),     // GPU DMA execution on going
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    .vid_ram_addr_o          (vid_ram_addr_o        ),     // Video-RAM address
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    .vid_ram_din_o           (vid_ram_din_o         ),     // Video-RAM data
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    .vid_ram_wen_o           (vid_ram_wen_o         ),     // Video-RAM write strobe (active low)
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    .vid_ram_cen_o           (vid_ram_cen_o         ),     // Video-RAM chip enable (active low)
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// INPUTs
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    .mclk                    (mclk                  ),     // Main system clock
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    .puc_rst                 (puc_rst               ),     // Main system reset
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    .cfg_dst_px_addr_i       (cfg_dst_px_addr       ),     // Destination pixel address configuration
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    .cfg_dst_cl_swp_i        (cfg_dst_cl_swp        ),     // Destination Column/Line-Swap configuration
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    .cfg_dst_x_swp_i         (cfg_dst_x_swp         ),     // Destination X-Swap configuration
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    .cfg_dst_y_swp_i         (cfg_dst_y_swp         ),     // Destination Y-Swap configuration
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    .cfg_fill_color_i        (cfg_fill_color        ),     // Fill color (for rectangle fill operation)
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    .cfg_pix_op_sel_i        (cfg_pix_op_sel        ),     // Pixel operation to be performed during the copy
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    .cfg_rec_width_i         (cfg_rec_width         ),     // Rectangle width configuration
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    .cfg_rec_height_i        (cfg_rec_height        ),     // Rectangle height configuration
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    .cfg_src_px_addr_i       (cfg_src_px_addr       ),     // Source pixel address configuration
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    .cfg_src_cl_swp_i        (cfg_src_cl_swp        ),     // Source Column/Line-Swap configuration
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    .cfg_src_x_swp_i         (cfg_src_x_swp         ),     // Source X-Swap configuration
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    .cfg_src_y_swp_i         (cfg_src_y_swp         ),     // Source Y-Swap configuration
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    .cfg_transparent_color_i (cfg_transparent_color ),     // Transparent color (for rectangle transparent copy operation)
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    .display_width_i         (display_width_i       ),     // Display width
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    .gfx_mode_i              (gfx_mode_i            ),     // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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    .gpu_enable_i            (gpu_enable_i          ),     // GPU enable
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    .exec_fill_i             (exec_fill             ),     // Rectangle fill on going
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    .exec_copy_i             (exec_copy             ),     // Rectangle copy on going
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    .exec_copy_trans_i       (exec_copy_trans       ),     // Rectangle transparent copy on going
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    .trig_exec_i             (trig_exec             ),     // Trigger rectangle execution
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    .vid_ram_dout_i          (vid_ram_dout_i        ),     // Video-RAM data input
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    .vid_ram_dout_rdy_nxt_i  (vid_ram_dout_rdy_nxt_i)      // Video-RAM data output ready during next cycle
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);
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endmodule // ogfx_gpu
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_undefines.v"
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`endif

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