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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [opengfx430/] [ogfx_gpu_dma_addr.v] - Blame information for rev 221

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1 221 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ogfx_gpu_dma_addr.v
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//
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// *Module Description:
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//                      Compute next Video-Ram address
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module  ogfx_gpu_dma_addr (
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// OUTPUTs
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    vid_ram_addr_nxt_o,                       // Next Video-RAM address
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// INPUTs
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    mclk,                                     // Main system clock
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    puc_rst,                                  // Main system reset
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    display_width_i,                          // Display width
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    gfx_mode_1_bpp_i,                         // Graphic mode  1 bpp resolution
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    gfx_mode_2_bpp_i,                         // Graphic mode  2 bpp resolution
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    gfx_mode_4_bpp_i,                         // Graphic mode  4 bpp resolution
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    gfx_mode_8_bpp_i,                         // Graphic mode  8 bpp resolution
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    gfx_mode_16_bpp_i,                        // Graphic mode 16 bpp resolution
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    vid_ram_addr_i,                           // Video-RAM address
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    vid_ram_addr_init_i,                      // Video-RAM address initialization
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    vid_ram_addr_step_i,                      // Video-RAM address step
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    vid_ram_width_i,                          // Video-RAM width
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    vid_ram_win_x_swap_i,                     // Video-RAM X-Swap configuration
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    vid_ram_win_y_swap_i,                     // Video-RAM Y-Swap configuration
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    vid_ram_win_cl_swap_i                     // Video-RAM CL-Swap configuration
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);
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// OUTPUTs
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//=========
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output   [`APIX_MSB:0] vid_ram_addr_nxt_o;    //  Next Video-RAM address
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// INPUTs
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//=========
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input                  mclk;                  // Main system clock
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input                  puc_rst;               // Main system reset
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input    [`LPIX_MSB:0] display_width_i;       // Display width
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input                  gfx_mode_1_bpp_i;      // Graphic mode  1 bpp resolution
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input                  gfx_mode_2_bpp_i;      // Graphic mode  2 bpp resolution
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input                  gfx_mode_4_bpp_i;      // Graphic mode  4 bpp resolution
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input                  gfx_mode_8_bpp_i;      // Graphic mode  8 bpp resolution
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input                  gfx_mode_16_bpp_i;     // Graphic mode 16 bpp resolution
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input    [`APIX_MSB:0] vid_ram_addr_i;        // Video-RAM address
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input                  vid_ram_addr_init_i;   // Video-RAM address initialization
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input                  vid_ram_addr_step_i;   // Video-RAM address step
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input    [`LPIX_MSB:0] vid_ram_width_i;       // Video-RAM width
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input                  vid_ram_win_x_swap_i;  // Video-RAM X-Swap configuration
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input                  vid_ram_win_y_swap_i;  // Video-RAM Y-Swap configuration
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input                  vid_ram_win_cl_swap_i; // Video-RAM CL-Swap configuration
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//=============================================================================
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// 1)  COMPUTE NEXT MEMORY ACCESS
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//=============================================================================
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reg    [`APIX_MSB:0] vid_ram_line_addr;
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reg    [`LPIX_MSB:0] vid_ram_column_count;
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// Detect when the current line refresh is done
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wire                 vid_ram_line_done    = vid_ram_addr_step_i & (vid_ram_column_count==(vid_ram_width_i-{{`LPIX_MSB{1'b0}}, 1'b1}));
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// Mux between initialization value and display width
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wire   [`LPIX_MSB:0] vid_ram_length_mux   = vid_ram_addr_init_i ? vid_ram_width_i : display_width_i ;
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// Align depending on graphic mode
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wire [`LPIX_MSB+4:0] vid_ram_length_align =  {`LPIX_MSB+5{gfx_mode_1_bpp_i }} & {4'b0000, vid_ram_length_mux[`LPIX_MSB:0]         } |
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                                             {`LPIX_MSB+5{gfx_mode_2_bpp_i }} & {3'b000,  vid_ram_length_mux[`LPIX_MSB:0], 1'b0   } |
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                                             {`LPIX_MSB+5{gfx_mode_4_bpp_i }} & {2'b00,   vid_ram_length_mux[`LPIX_MSB:0], 2'b00  } |
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                                             {`LPIX_MSB+5{gfx_mode_8_bpp_i }} & {1'b0,    vid_ram_length_mux[`LPIX_MSB:0], 3'b000 } |
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                                             {`LPIX_MSB+5{gfx_mode_16_bpp_i}} & {         vid_ram_length_mux[`LPIX_MSB:0], 4'b0000} ;
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wire   [`APIX_MSB:0] plus_one_val         =  {`APIX_MSB+1{gfx_mode_1_bpp_i }} & {4'b0000, {{`VRAM_MSB{1'b0}}, 1'b1}               } |
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                                             {`APIX_MSB+1{gfx_mode_2_bpp_i }} & {3'b000,  {{`VRAM_MSB{1'b0}}, 1'b1},       1'b0   } |
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                                             {`APIX_MSB+1{gfx_mode_4_bpp_i }} & {2'b00,   {{`VRAM_MSB{1'b0}}, 1'b1},       2'b00  } |
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                                             {`APIX_MSB+1{gfx_mode_8_bpp_i }} & {1'b0,    {{`VRAM_MSB{1'b0}}, 1'b1},       3'b000 } |
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                                             {`APIX_MSB+1{gfx_mode_16_bpp_i}} & {         {{`VRAM_MSB{1'b0}}, 1'b1},       4'b0000} ;
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// Zero extension for LINT cleanup
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wire [`APIX_MSB*3:0] vid_ram_length_norm  =  {{`APIX_MSB*3-`LPIX_MSB-4{1'b0}}, vid_ram_length_align};
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// Select base address for next calculation
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wire   [`APIX_MSB:0] next_base_addr       =  (vid_ram_addr_init_i | ~vid_ram_line_done) ? vid_ram_addr_i    :
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                                                                                          vid_ram_line_addr ;
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// Compute next address
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wire   [`APIX_MSB:0] next_addr            =   next_base_addr
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                                            + (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
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                                            - (vid_ram_length_norm[`APIX_MSB:0] & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_y_swap_i &  (vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
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                                            + (plus_one_val                     & {`APIX_MSB+1{~vid_ram_addr_init_i ? (~vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}})
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                                            - (plus_one_val                     & {`APIX_MSB+1{~vid_ram_addr_init_i ? ( vid_ram_win_x_swap_i & ~(vid_ram_win_cl_swap_i ^ vid_ram_line_done)) : 1'b0}});
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wire                 update_line_addr     =   vid_ram_addr_init_i | vid_ram_line_done;
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wire                 update_pixel_addr    =   update_line_addr    | vid_ram_addr_step_i;
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// Start RAM address of currentely refreshed line
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always @(posedge mclk or posedge puc_rst)
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  if (puc_rst)               vid_ram_line_addr  <=  {`APIX_MSB+1{1'b0}};
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  else if (update_line_addr) vid_ram_line_addr  <=  next_addr;
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// Current RAM address of the currentely refreshed pixel
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assign vid_ram_addr_nxt_o = update_pixel_addr ? next_addr : vid_ram_addr_i;
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// Count the pixel number in the current line
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// (used to detec the end of a line)
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always @(posedge mclk or posedge puc_rst)
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  if (puc_rst)                   vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
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  else if (vid_ram_addr_init_i)  vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
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  else if (vid_ram_line_done)    vid_ram_column_count  <=  {`LPIX_MSB+1{1'b0}};
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  else if (vid_ram_addr_step_i)  vid_ram_column_count  <=  vid_ram_column_count + {{`LPIX_MSB{1'b0}}, 1'b1};
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endmodule // ogfx_calc_vram_addr
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_undefines.v"
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`endif

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