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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [opengfx430/] [ogfx_gpu_reg.v] - Blame information for rev 221

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1 221 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2015 Authors
3
//
4
// This source file may be used and distributed without restriction provided
5
// that this copyright statement is not removed from the file and that any
6
// derivative work contains the original copyright notice and the associated
7
// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
17
// License for more details.
18
//
19
// You should have received a copy of the GNU Lesser General Public License
20
// along with this source; if not, write to the Free Software Foundation,
21
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25
// *File Name: ogfx_gpu_reg.v
26
//
27
// *Module Description:
28
//                      Configuration registers of the Graphic-Processing unit
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34
// $Rev$
35
// $LastChangedBy$
36
// $LastChangedDate$
37
//----------------------------------------------------------------------------
38
`ifdef OGFX_NO_INCLUDE
39
`else
40
`include "openGFX430_defines.v"
41
`endif
42
 
43
module  ogfx_gpu_reg (
44
 
45
// OUTPUTs
46
    cfg_dst_px_addr_o,                            // Destination pixel address configuration
47
    cfg_dst_cl_swp_o,                             // Destination Column/Line-Swap configuration
48
    cfg_dst_x_swp_o,                              // Destination X-Swap configuration
49
    cfg_dst_y_swp_o,                              // Destination Y-Swap configuration
50
    cfg_fill_color_o,                             // Fill color (for rectangle fill operation)
51
    cfg_pix_op_sel_o,                             // Pixel operation to be performed during the copy
52
    cfg_rec_width_o,                              // Rectangle width configuration
53
    cfg_rec_height_o,                             // Rectangle height configuration
54
    cfg_src_px_addr_o,                            // Source pixel address configuration
55
    cfg_src_cl_swp_o,                             // Source Column/Line-Swap configuration
56
    cfg_src_x_swp_o,                              // Source X-Swap configuration
57
    cfg_src_y_swp_o,                              // Source Y-Swap configuration
58
    cfg_transparent_color_o,                      // Transparent color (for rectangle transparent copy operation)
59
 
60
    gpu_cmd_done_evt_o,                           // GPU command done event
61
    gpu_cmd_error_evt_o,                          // GPU command error event
62
    gpu_get_data_o,                               // GPU get next data
63
 
64
    exec_fill_o,                                  // Rectangle fill on going
65
    exec_copy_o,                                  // Rectangle copy on going
66
    exec_copy_trans_o,                            // Rectangle transparent copy on going
67
    trig_exec_o,                                  // Trigger rectangle execution
68
 
69
// INPUTs
70
    mclk,                                         // Main system clock
71
    puc_rst,                                      // Main system reset
72
 
73
    gpu_data_i,                                   // GPU data
74
    gpu_data_avail_i,                             // GPU data available
75
    gfx_mode_i,                                   // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
76
    gpu_enable_i,                                 // GPU enable
77
 
78
    gpu_exec_done_i                               // GPU execution done
79
);
80
 
81
// OUTPUTs
82
//=========
83
output [`APIX_MSB:0] cfg_dst_px_addr_o;           // Destination pixel address configuration
84
output               cfg_dst_cl_swp_o;            // Destination Column/Line-Swap configuration
85
output               cfg_dst_x_swp_o;             // Destination X-Swap configuration
86
output               cfg_dst_y_swp_o;             // Destination Y-Swap configuration
87
output        [15:0] cfg_fill_color_o;            // Fill color (for rectangle fill operation)
88
output         [3:0] cfg_pix_op_sel_o;            // Pixel operation to be performed during the copy
89
output [`LPIX_MSB:0] cfg_rec_width_o;             // Rectangle width configuration
90
output [`LPIX_MSB:0] cfg_rec_height_o;            // Rectangle height configuration
91
output [`APIX_MSB:0] cfg_src_px_addr_o;           // Source pixel address configuration
92
output               cfg_src_cl_swp_o;            // Source Column/Line-Swap configuration
93
output               cfg_src_x_swp_o;             // Source X-Swap configuration
94
output               cfg_src_y_swp_o;             // Source Y-Swap configuration
95
output        [15:0] cfg_transparent_color_o;     // Transparent color (for rectangle transparent copy operation)
96
 
97
output               gpu_cmd_done_evt_o;          // GPU command done event
98
output               gpu_cmd_error_evt_o;         // GPU command error event
99
output               gpu_get_data_o;              // GPU get next data
100
 
101
output               exec_fill_o;                 // Rectangle fill on going
102
output               exec_copy_o;                 // Rectangle copy on going
103
output               exec_copy_trans_o;           // Rectangle transparent copy on going
104
output               trig_exec_o;                 // Trigger rectangle execution
105
 
106
// INPUTs
107
//=========
108
input                mclk;                        // Main system clock
109
input                puc_rst;                     // Main system reset
110
 
111
input         [15:0] gpu_data_i;                  // GPU data
112
input                gpu_data_avail_i;            // GPU data available
113
input          [2:0] gfx_mode_i;                  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
114
input                gpu_enable_i;                // GPU enable
115
 
116
input                gpu_exec_done_i;             // GPU execution done
117
 
118
//=============================================================================
119
// 1)  WIRE, REGISTERS AND PARAMETER DECLARATION
120
//=============================================================================
121
 
122
// Video modes decoding
123
wire                 gfx_mode_1_bpp    =  (gfx_mode_i == 3'b000);
124
wire                 gfx_mode_2_bpp    =  (gfx_mode_i == 3'b001);
125
wire                 gfx_mode_4_bpp    =  (gfx_mode_i == 3'b010);
126
wire                 gfx_mode_8_bpp    =  (gfx_mode_i == 3'b011);
127
wire                 gfx_mode_16_bpp   = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);
128
 
129
// Remaining wires/registers
130
reg                  exec_fill_o;
131
reg                  exec_copy_o;
132
reg                  exec_copy_trans_o;
133
 
134
reg            [1:0] src_offset_sel;
135
reg                  src_x_swp;
136
reg                  src_y_swp;
137
reg                  src_cl_swp;
138
reg            [3:0] pix_op_sel;
139
reg            [1:0] dst_offset_sel;
140
reg                  dst_x_swp;
141
reg                  dst_y_swp;
142
reg                  dst_cl_swp;
143
 
144
reg            [3:0] reg_access;
145
wire           [3:0] reg_access_nxt;
146
 
147
reg           [15:0] fill_color;
148
reg    [`LPIX_MSB:0] rec_width;
149
reg    [`LPIX_MSB:0] rec_height;
150
wire   [`APIX_MSB:0] src_px_addr;
151
wire   [`APIX_MSB:0] src_px_addr_align;
152
wire   [`APIX_MSB:0] dst_px_addr;
153
wire   [`APIX_MSB:0] dst_px_addr_align;
154
wire   [`APIX_MSB:0] of0_addr;
155
wire   [`APIX_MSB:0] of1_addr;
156
wire   [`APIX_MSB:0] of2_addr;
157
wire   [`APIX_MSB:0] of3_addr;
158
reg           [15:0] transparent_color;
159
 
160
wire   [`APIX_MSB:0] src_offset_addr;
161
wire   [`APIX_MSB:0] dst_offset_addr;
162
 
163
 
164
//=============================================================================
165
// 2)  GPU COMMAND STATE MACHINE
166
//=============================================================================
167
//
168
// EXEC_FILL        - Execute rectangle fill command
169
//                    {2'b00, reserved<4:0>,                                     pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
170
//                    {fill_color[15:0]}
171
//
172
// EXEC_COPY        - Execute rectangle copy command
173
//                    {2'b01, src_offset[1:0], src_X-Swp, src_Y-Swp, src_CL-Swp, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
174
//
175
// EXEC_COPY_TRANS  - Execute rectangle copy with transparency command
176
//                    {2'b10, src_offset[1:0], src_X-Swp, src_Y-Swp, src_CL-Swp, pxop[3:0], dst_offset[1:0], dst_X-Swp, dst_Y-Swp, dst_CL-Swp}
177
//
178
// REC_WIDTH        - Set rectangle width
179
//                    {4'b1100, width[11:0]}
180
//
181
// REC_HEIGHT       - Set rectangle height
182
//                    {4'b1101, height[11:0]}
183
//
184
// SRC_PX_ADDR      - Set source address
185
//                    {4'b1111, 2'b10, 10'b0000000000}
186
//                    {addr[15:0]                    }
187
//                    {addr[31:16]                   }
188
//
189
// DST_PX_ADDR      - Set destination address
190
//                    {4'b1111, 2'b10, 10'b0000000001}
191
//                    {addr[15:0]                    }
192
//                    {addr[31:16]                   }
193
//
194
// OF0_ADDR         - Set address offset 0
195
//                    {4'b1111, 2'b10, 10'b0000010000}
196
//                    {addr[15:0]                    }
197
//                    {addr[31:16]                   }
198
//
199
// OF1_ADDR         - Set address offset 1
200
//                    {4'b1111, 2'b10, 10'b0000010001}
201
//                    {addr[15:0]                    }
202
//                    {addr[31:16]                   }
203
//
204
// OF2_ADDR         - Set address offset 2
205
//                    {4'b1111, 2'b10, 10'b0000010010}
206
//                    {addr[15:0]                    }
207
//                    {addr[31:16]                   }
208
//
209
// OF3_ADDR         - Set address offset 3
210
//                    {4'b1111, 2'b10, 10'b0000010011}
211
//                    {addr[15:0]                    }
212
//                    {addr[31:16]                   }
213
//
214
// SET_FILL         - Set fill color
215
//                    {4'b1111, 2'b01, 10'b0000100000}
216
//                    {fill_color[15:0]              }
217
//
218
// SET_TRANSPARENT  - Set transparent color
219
//                    {4'b1111, 2'b01, 10'b0000100001}
220
//                    {transparent_color[15:0]       }
221
//
222
//-----------------------------------------------------------------------------
223
 
224
// State definition
225
parameter  CMD_WAIT         =  4'h0;
226
parameter  CMD_READ         =  4'h1;
227
parameter  DATA1B_WAIT      =  4'h2;
228
parameter  DATA1B_READ      =  4'h3;
229
parameter  DATA2B1_WAIT     =  4'h4;
230
parameter  DATA2B1_READ     =  4'h5;
231
parameter  DATA2B2_WAIT     =  4'h6;
232
parameter  DATA2B2_READ     =  4'h7;
233
parameter  EXEC_START       =  4'h8;
234
parameter  EXEC             =  4'h9;
235
parameter  ERROR            =  4'hA;
236
 
237
// State machine
238
reg  [3:0] gpu_state;
239
reg  [3:0] gpu_state_nxt;
240
 
241
// Arcs control
242
wire       cmd_available    =  gpu_data_avail_i;
243
 
244
wire       cmd_not_valid    = ((gpu_data_i[15:14]!= `OP_EXEC_FILL      ) &
245
                               (gpu_data_i[15:14]!= `OP_EXEC_COPY      ) &
246
                               (gpu_data_i[15:14]!= `OP_EXEC_COPY_TRANS) &
247
                               (gpu_data_i[15:12]!= `OP_REC_WIDTH      ) &
248
                               (gpu_data_i[15:12]!= `OP_REC_HEIGHT     ) &
249
                               (gpu_data_i[15:0] != `OP_SRC_PX_ADDR    ) &
250
                               (gpu_data_i[15:0] != `OP_DST_PX_ADDR    ) &
251
                               (gpu_data_i[15:0] != `OP_OF0_ADDR       ) &
252
                               (gpu_data_i[15:0] != `OP_OF1_ADDR       ) &
253
                               (gpu_data_i[15:0] != `OP_OF2_ADDR       ) &
254
                               (gpu_data_i[15:0] != `OP_OF3_ADDR       ) &
255
                               (gpu_data_i[15:0] != `OP_SET_FILL       ) &
256
                               (gpu_data_i[15:0] != `OP_SET_TRANSPARENT));
257
 
258
wire       cmd_has_1b_data  =  (gpu_data_i[15:14]== `OP_EXEC_FILL      ) |
259
                               (gpu_data_i[15:0] == `OP_SET_FILL       ) |
260
                               (gpu_data_i[15:0] == `OP_SET_TRANSPARENT);
261
 
262
wire       cmd_has_2b_data  =  (gpu_data_i[15:0] == `OP_SRC_PX_ADDR    ) |
263
                               (gpu_data_i[15:0] == `OP_DST_PX_ADDR    ) |
264
                               (gpu_data_i[15:0] == `OP_OF0_ADDR       ) |
265
                               (gpu_data_i[15:0] == `OP_OF1_ADDR       ) |
266
                               (gpu_data_i[15:0] == `OP_OF2_ADDR       ) |
267
                               (gpu_data_i[15:0] == `OP_OF3_ADDR       );
268
 
269
wire       cmd_has_exec     =  exec_fill_o | exec_copy_o | exec_copy_trans_o;
270
 
271
wire       data_available   =  gpu_data_avail_i;
272
 
273
 
274
// State transition
275
always @(gpu_state or cmd_available or cmd_not_valid or cmd_has_1b_data or cmd_has_2b_data or cmd_has_exec or data_available or gpu_exec_done_i)
276
  case (gpu_state)
277
    CMD_WAIT     : gpu_state_nxt =  cmd_available   ? CMD_READ     : CMD_WAIT     ;
278
    CMD_READ     : gpu_state_nxt =  cmd_not_valid   ? ERROR        :
279
                                    cmd_has_1b_data ? DATA1B_WAIT  :
280
                                    cmd_has_2b_data ? DATA2B1_WAIT :
281
                                    cmd_has_exec    ? EXEC_START   : CMD_WAIT     ;
282
 
283
    DATA1B_WAIT  : gpu_state_nxt =  data_available  ? DATA1B_READ  : DATA1B_WAIT  ;
284
    DATA1B_READ  : gpu_state_nxt =  cmd_has_exec    ? EXEC_START   : CMD_WAIT     ;
285
 
286
    DATA2B1_WAIT : gpu_state_nxt =  data_available  ? DATA2B1_READ : DATA2B1_WAIT ;
287
    DATA2B1_READ : gpu_state_nxt =                    DATA2B2_WAIT                ;
288
 
289
    DATA2B2_WAIT : gpu_state_nxt =  data_available  ? DATA2B2_READ : DATA2B2_WAIT ;
290
    DATA2B2_READ : gpu_state_nxt =  cmd_has_exec    ? EXEC_START   : CMD_WAIT     ;
291
 
292
    EXEC_START   : gpu_state_nxt =  gpu_exec_done_i ? CMD_WAIT     : EXEC         ;
293
    EXEC         : gpu_state_nxt =  gpu_exec_done_i ? CMD_WAIT     : EXEC         ;
294
    ERROR        : gpu_state_nxt =                    ERROR                       ;
295
  // pragma coverage off
296
    default      : gpu_state_nxt =                    CMD_WAIT                    ;
297
  // pragma coverage on
298
  endcase
299
 
300
 
301
// State machine
302
always @(posedge mclk or posedge puc_rst)
303
  if (puc_rst)            gpu_state <= CMD_WAIT;
304
  else if (~gpu_enable_i) gpu_state <= CMD_WAIT;
305
  else                    gpu_state <= gpu_state_nxt;
306
 
307
 
308
// Event generation, fifo data request
309
assign  gpu_cmd_done_evt_o  = (gpu_state!=ERROR) & (gpu_state!=CMD_WAIT) & (gpu_state_nxt==CMD_WAIT);
310
assign  gpu_cmd_error_evt_o = (gpu_state==ERROR);
311
assign  gpu_get_data_o      = (gpu_state==CMD_READ) | (gpu_state==DATA1B_READ) | (gpu_state==DATA2B1_READ) | (gpu_state==DATA2B2_READ);
312
 
313
// Execution triggers
314
assign  trig_exec_o         = (exec_fill_o      |
315
                               exec_copy_o      |
316
                               exec_copy_trans_o) & (gpu_state==EXEC_START);
317
 
318
 
319
//=============================================================================
320
// 3)  CONFIGURATION REGISTERS
321
//=============================================================================
322
 
323
// Detect execution commands
324
always @(posedge mclk or posedge puc_rst)
325
  if (puc_rst)                                    exec_fill_o       <= 1'b0;
326
  else if ((gpu_state==CMD_WAIT) & cmd_available) exec_fill_o       <= (gpu_data_i[15:14]==`OP_EXEC_FILL);
327
  else if ((gpu_state_nxt==CMD_WAIT)            ) exec_fill_o       <= 1'b0;
328
 
329
always @(posedge mclk or posedge puc_rst)
330
  if (puc_rst)                                    exec_copy_o       <= 1'b0;
331
  else if ((gpu_state==CMD_WAIT) & cmd_available) exec_copy_o       <= (gpu_data_i[15:14]==`OP_EXEC_COPY);
332
  else if ((gpu_state_nxt==CMD_WAIT)            ) exec_copy_o       <= 1'b0;
333
 
334
always @(posedge mclk or posedge puc_rst)
335
  if (puc_rst)                                    exec_copy_trans_o <= 1'b0;
336
  else if ((gpu_state==CMD_WAIT) & cmd_available) exec_copy_trans_o <= (gpu_data_i[15:14]==`OP_EXEC_COPY_TRANS);
337
  else if ((gpu_state_nxt==CMD_WAIT)            ) exec_copy_trans_o <= 1'b0;
338
 
339
// Detect register accesses
340
parameter REG_EXEC_FILL       = 4'h1;
341
parameter REG_REC_WIDTH       = 4'h2;
342
parameter REG_REC_HEIGHT      = 4'h3;
343
parameter REG_SRC_PX_ADDR     = 4'h4;
344
parameter REG_DST_PX_ADDR     = 4'h5;
345
parameter REG_OF0_ADDR        = 4'h6;
346
parameter REG_OF1_ADDR        = 4'h7;
347
parameter REG_OF2_ADDR        = 4'h8;
348
parameter REG_OF3_ADDR        = 4'h9;
349
parameter REG_SET_FILL        = 4'hA;
350
parameter REG_SET_TRANSPARENT = 4'hB;
351
 
352
assign    reg_access_nxt      = ({4{gpu_data_i[15:14]== `OP_EXEC_FILL      }} & REG_EXEC_FILL      ) |
353
                                ({4{gpu_data_i[15:12]== `OP_REC_WIDTH      }} & REG_REC_WIDTH      ) |
354
                                ({4{gpu_data_i[15:12]== `OP_REC_HEIGHT     }} & REG_REC_HEIGHT     ) |
355
                                ({4{gpu_data_i[15:0] == `OP_SRC_PX_ADDR    }} & REG_SRC_PX_ADDR    ) |
356
                                ({4{gpu_data_i[15:0] == `OP_DST_PX_ADDR    }} & REG_DST_PX_ADDR    ) |
357
                                ({4{gpu_data_i[15:0] == `OP_OF0_ADDR       }} & REG_OF0_ADDR       ) |
358
                                ({4{gpu_data_i[15:0] == `OP_OF1_ADDR       }} & REG_OF1_ADDR       ) |
359
                                ({4{gpu_data_i[15:0] == `OP_OF2_ADDR       }} & REG_OF2_ADDR       ) |
360
                                ({4{gpu_data_i[15:0] == `OP_OF3_ADDR       }} & REG_OF3_ADDR       ) |
361
                                ({4{gpu_data_i[15:0] == `OP_SET_FILL       }} & REG_SET_FILL       ) |
362
                                ({4{gpu_data_i[15:0] == `OP_SET_TRANSPARENT}} & REG_SET_TRANSPARENT) ;
363
 
364
always @(posedge mclk or posedge puc_rst)
365
  if (puc_rst)                      reg_access <= 4'h0;
366
  else if (gpu_state==CMD_READ)     reg_access <= reg_access_nxt;
367
  else if (gpu_state_nxt==CMD_WAIT) reg_access <= 4'h0;
368
 
369
 
370
//=============================================================================
371
// 4)  CONFIGURATION REGISTERS
372
//=============================================================================
373
 
374
//------------------------------------------------
375
// EXECUTION CONFIG Register
376
//------------------------------------------------
377
 
378
wire  exec_all_cfg_wr = (exec_fill_o | exec_copy_o | exec_copy_trans_o) & (gpu_state==CMD_READ);
379
wire  exec_src_cfg_wr = (              exec_copy_o | exec_copy_trans_o) & (gpu_state==CMD_READ);
380
 
381
always @ (posedge mclk or posedge puc_rst)
382
  if (puc_rst)
383
    begin
384
       src_offset_sel <= 2'b00;
385
       src_x_swp      <= 1'b0;
386
       src_y_swp      <= 1'b0;
387
       src_cl_swp     <= 1'b0;
388
    end
389
  else if (exec_src_cfg_wr)
390
    begin
391
       src_offset_sel <= gpu_data_i[13:12];
392
       src_x_swp      <= gpu_data_i[11];
393
       src_y_swp      <= gpu_data_i[10];
394
       src_cl_swp     <= gpu_data_i[9];
395
    end
396
 
397
always @ (posedge mclk or posedge puc_rst)
398
  if (puc_rst)
399
    begin
400
       pix_op_sel     <= 4'b0000;
401
       dst_offset_sel <= 2'b00;
402
       dst_x_swp      <= 1'b0;
403
       dst_y_swp      <= 1'b0;
404
       dst_cl_swp     <= 1'b0;
405
    end
406
  else if (exec_all_cfg_wr)
407
    begin
408
       pix_op_sel     <= gpu_data_i[8:5];
409
       dst_offset_sel <= gpu_data_i[4:3];
410
       dst_x_swp      <= gpu_data_i[2];
411
       dst_y_swp      <= gpu_data_i[1];
412
       dst_cl_swp     <= gpu_data_i[0];
413
    end
414
 
415
assign cfg_src_x_swp_o  = src_x_swp;
416
assign cfg_src_y_swp_o  = src_y_swp;
417
assign cfg_src_cl_swp_o = src_cl_swp;
418
assign cfg_pix_op_sel_o = pix_op_sel;
419
assign cfg_dst_x_swp_o  = dst_x_swp;
420
assign cfg_dst_y_swp_o  = dst_y_swp;
421
assign cfg_dst_cl_swp_o = dst_cl_swp;
422
 
423
//------------------------------------------------
424
// FILL_COLOR Register
425
//------------------------------------------------
426
 
427
wire  fill_color_wr = ((reg_access==REG_EXEC_FILL) |
428
                       (reg_access==REG_SET_FILL ) ) & (gpu_state==DATA1B_READ);
429
 
430
always @ (posedge mclk or posedge puc_rst)
431
  if (puc_rst)            fill_color <=  16'h0000;
432
  else if (fill_color_wr) fill_color <=  gpu_data_i;
433
 
434
assign cfg_fill_color_o = fill_color;
435
 
436
//------------------------------------------------
437
// REC_WIDTH Register
438
//------------------------------------------------
439
 
440
wire               rec_width_wr = (reg_access_nxt==REG_REC_WIDTH) & (gpu_state==CMD_READ);
441
 
442
wire [`LPIX_MSB:0] rec_w_h_nxt  = (|gpu_data_i[`LPIX_MSB:0]) ? gpu_data_i[`LPIX_MSB:0] :
443
                                                               {{`LPIX_MSB{1'b0}}, 1'b1};
444
 
445
 
446
always @ (posedge mclk or posedge puc_rst)
447
  if (puc_rst)           rec_width <=  {{`LPIX_MSB{1'b0}}, 1'b1};
448
  else if (rec_width_wr) rec_width <=  rec_w_h_nxt;
449
 
450
assign cfg_rec_width_o = rec_width;
451
 
452
//------------------------------------------------
453
// REC_HEIGHT Register
454
//------------------------------------------------
455
 
456
wire  rec_height_wr = (reg_access_nxt==REG_REC_HEIGHT) & (gpu_state==CMD_READ);
457
 
458
always @ (posedge mclk or posedge puc_rst)
459
  if (puc_rst)            rec_height <=  {{`LPIX_MSB{1'b0}}, 1'b1};
460
  else if (rec_height_wr) rec_height <=  rec_w_h_nxt;
461
 
462
assign cfg_rec_height_o = rec_height;
463
 
464
//------------------------------------------------
465
// SRC_PX_ADDR_HI Register
466
//------------------------------------------------
467
`ifdef VRAM_BIGGER_4_KW
468
reg [`APIX_HI_MSB:0] src_px_addr_hi;
469
 
470
wire                 src_px_addr_hi_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B2_READ);
471
 
472
always @ (posedge mclk or posedge puc_rst)
473
  if (puc_rst)                src_px_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
474
  else if (src_px_addr_hi_wr) src_px_addr_hi <=  gpu_data_i[`APIX_HI_MSB:0];
475
`endif
476
 
477
//------------------------------------------------
478
// SRC_PX_ADDR_LO Register
479
//------------------------------------------------
480
reg [`APIX_LO_MSB:0] src_px_addr_lo;
481
 
482
wire                 src_px_addr_lo_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B1_READ);
483
 
484
always @ (posedge mclk or posedge puc_rst)
485
  if (puc_rst)                src_px_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
486
  else if (src_px_addr_lo_wr) src_px_addr_lo <=  gpu_data_i[`APIX_LO_MSB:0];
487
 
488
`ifdef VRAM_BIGGER_4_KW
489
assign      src_px_addr  = {src_px_addr_hi[`APIX_HI_MSB:0], src_px_addr_lo};
490
`else
491
assign      src_px_addr  = {src_px_addr_lo[`APIX_LO_MSB:0]};
492
`endif
493
 
494
assign src_px_addr_align = src_px_addr + src_offset_addr;
495
assign cfg_src_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {src_px_addr_align[`APIX_MSB:0]           } |
496
                           {`APIX_MSB+1{gfx_mode_2_bpp }} & {src_px_addr_align[`APIX_MSB-1:0], 1'b0   } |
497
                           {`APIX_MSB+1{gfx_mode_4_bpp }} & {src_px_addr_align[`APIX_MSB-2:0], 2'b00  } |
498
                           {`APIX_MSB+1{gfx_mode_8_bpp }} & {src_px_addr_align[`APIX_MSB-3:0], 3'b000 } |
499
                           {`APIX_MSB+1{gfx_mode_16_bpp}} & {src_px_addr_align[`APIX_MSB-4:0], 4'b0000} ;
500
 
501
//------------------------------------------------
502
// DST_PX_ADDR_HI Register
503
//------------------------------------------------
504
`ifdef VRAM_BIGGER_4_KW
505
reg [`APIX_HI_MSB:0] dst_px_addr_hi;
506
 
507
wire                 dst_px_addr_hi_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B2_READ);
508
 
509
always @ (posedge mclk or posedge puc_rst)
510
  if (puc_rst)                dst_px_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
511
  else if (dst_px_addr_hi_wr) dst_px_addr_hi <=  gpu_data_i[`APIX_HI_MSB:0];
512
`endif
513
 
514
//------------------------------------------------
515
// DST_PX_ADDR_LO Register
516
//------------------------------------------------
517
reg [`APIX_LO_MSB:0] dst_px_addr_lo;
518
 
519
wire                 dst_px_addr_lo_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B1_READ);
520
 
521
always @ (posedge mclk or posedge puc_rst)
522
  if (puc_rst)                dst_px_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
523
  else if (dst_px_addr_lo_wr) dst_px_addr_lo <=  gpu_data_i[`APIX_LO_MSB:0];
524
 
525
`ifdef VRAM_BIGGER_4_KW
526
assign      dst_px_addr  = {dst_px_addr_hi[`APIX_HI_MSB:0], dst_px_addr_lo};
527
`else
528
assign      dst_px_addr  = {dst_px_addr_lo[`APIX_LO_MSB:0]};
529
`endif
530
 
531
assign dst_px_addr_align = dst_px_addr + dst_offset_addr;
532
assign cfg_dst_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {dst_px_addr_align[`APIX_MSB:0]           } |
533
                           {`APIX_MSB+1{gfx_mode_2_bpp }} & {dst_px_addr_align[`APIX_MSB-1:0], 1'b0   } |
534
                           {`APIX_MSB+1{gfx_mode_4_bpp }} & {dst_px_addr_align[`APIX_MSB-2:0], 2'b00  } |
535
                           {`APIX_MSB+1{gfx_mode_8_bpp }} & {dst_px_addr_align[`APIX_MSB-3:0], 3'b000 } |
536
                           {`APIX_MSB+1{gfx_mode_16_bpp}} & {dst_px_addr_align[`APIX_MSB-4:0], 4'b0000} ;
537
 
538
//------------------------------------------------
539
// OF0_ADDR_HI Register
540
//------------------------------------------------
541
`ifdef VRAM_BIGGER_4_KW
542
reg [`APIX_HI_MSB:0] of0_addr_hi;
543
 
544
wire                 of0_addr_hi_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B2_READ);
545
 
546
always @ (posedge mclk or posedge puc_rst)
547
  if (puc_rst)             of0_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
548
  else if (of0_addr_hi_wr) of0_addr_hi <=  gpu_data_i[`APIX_HI_MSB:0];
549
`endif
550
 
551
//------------------------------------------------
552
// OF0_ADDR_LO Register
553
//------------------------------------------------
554
reg [`APIX_LO_MSB:0] of0_addr_lo;
555
 
556
wire                 of0_addr_lo_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B1_READ);
557
 
558
always @ (posedge mclk or posedge puc_rst)
559
  if (puc_rst)             of0_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
560
  else if (of0_addr_lo_wr) of0_addr_lo <=  gpu_data_i[`APIX_LO_MSB:0];
561
 
562
`ifdef VRAM_BIGGER_4_KW
563
assign      of0_addr  = {of0_addr_hi[`APIX_HI_MSB:0], of0_addr_lo};
564
`else
565
assign      of0_addr  = {of0_addr_lo[`APIX_LO_MSB:0]};
566
`endif
567
 
568
//------------------------------------------------
569
// OF1_ADDR_HI Register
570
//------------------------------------------------
571
`ifdef VRAM_BIGGER_4_KW
572
reg [`APIX_HI_MSB:0] of1_addr_hi;
573
 
574
wire                 of1_addr_hi_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B2_READ);
575
 
576
always @ (posedge mclk or posedge puc_rst)
577
  if (puc_rst)             of1_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
578
  else if (of1_addr_hi_wr) of1_addr_hi <=  gpu_data_i[`APIX_HI_MSB:0];
579
`endif
580
 
581
//------------------------------------------------
582
// OF1_ADDR_LO Register
583
//------------------------------------------------
584
reg [`APIX_LO_MSB:0] of1_addr_lo;
585
 
586
wire                 of1_addr_lo_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B1_READ);
587
 
588
always @ (posedge mclk or posedge puc_rst)
589
  if (puc_rst)             of1_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
590
  else if (of1_addr_lo_wr) of1_addr_lo <=  gpu_data_i[`APIX_LO_MSB:0];
591
 
592
`ifdef VRAM_BIGGER_4_KW
593
assign      of1_addr  = {of1_addr_hi[`APIX_HI_MSB:0], of1_addr_lo};
594
`else
595
assign      of1_addr  = {of1_addr_lo[`APIX_LO_MSB:0]};
596
`endif
597
 
598
//------------------------------------------------
599
// OF2_ADDR_HI Register
600
//------------------------------------------------
601
`ifdef VRAM_BIGGER_4_KW
602
reg [`APIX_HI_MSB:0] of2_addr_hi;
603
 
604
wire                 of2_addr_hi_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B2_READ);
605
 
606
always @ (posedge mclk or posedge puc_rst)
607
  if (puc_rst)             of2_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
608
  else if (of2_addr_hi_wr) of2_addr_hi <=  gpu_data_i[`APIX_HI_MSB:0];
609
`endif
610
 
611
//------------------------------------------------
612
// OF2_ADDR_LO Register
613
//------------------------------------------------
614
reg [`APIX_LO_MSB:0] of2_addr_lo;
615
 
616
wire                 of2_addr_lo_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B1_READ);
617
 
618
always @ (posedge mclk or posedge puc_rst)
619
  if (puc_rst)             of2_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
620
  else if (of2_addr_lo_wr) of2_addr_lo <=  gpu_data_i[`APIX_LO_MSB:0];
621
 
622
`ifdef VRAM_BIGGER_4_KW
623
assign      of2_addr  = {of2_addr_hi[`APIX_HI_MSB:0], of2_addr_lo};
624
`else
625
assign      of2_addr  = {of2_addr_lo[`APIX_LO_MSB:0]};
626
`endif
627
 
628
//------------------------------------------------
629
// OF3_ADDR_HI Register
630
//------------------------------------------------
631
`ifdef VRAM_BIGGER_4_KW
632
reg [`APIX_HI_MSB:0] of3_addr_hi;
633
 
634
wire                 of3_addr_hi_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B2_READ);
635
 
636
always @ (posedge mclk or posedge puc_rst)
637
  if (puc_rst)             of3_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
638
  else if (of3_addr_hi_wr) of3_addr_hi <=  gpu_data_i[`APIX_HI_MSB:0];
639
`endif
640
 
641
//------------------------------------------------
642
// OF3_ADDR_LO Register
643
//------------------------------------------------
644
reg [`APIX_LO_MSB:0] of3_addr_lo;
645
 
646
wire                 of3_addr_lo_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B1_READ);
647
 
648
always @ (posedge mclk or posedge puc_rst)
649
  if (puc_rst)             of3_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
650
  else if (of3_addr_lo_wr) of3_addr_lo <=  gpu_data_i[`APIX_LO_MSB:0];
651
 
652
`ifdef VRAM_BIGGER_4_KW
653
assign      of3_addr  = {of3_addr_hi[`APIX_HI_MSB:0], of3_addr_lo};
654
`else
655
assign      of3_addr  = {of3_addr_lo[`APIX_LO_MSB:0]};
656
`endif
657
 
658
// Offset address selection
659
assign src_offset_addr    = (src_offset_sel==2'h0) ? of0_addr :
660
                            (src_offset_sel==2'h1) ? of1_addr :
661
                            (src_offset_sel==2'h2) ? of2_addr : of3_addr;
662
 
663
assign dst_offset_addr    = (dst_offset_sel==2'h0) ? of0_addr :
664
                            (dst_offset_sel==2'h1) ? of1_addr :
665
                            (dst_offset_sel==2'h2) ? of2_addr : of3_addr;
666
 
667
 
668
//------------------------------------------------
669
// TRANSPARENT_COLOR Register
670
//------------------------------------------------
671
 
672
wire  transparent_color_wr = (reg_access==REG_SET_TRANSPARENT) & (gpu_state==DATA1B_READ);
673
 
674
always @ (posedge mclk or posedge puc_rst)
675
  if (puc_rst)                   transparent_color <=  16'h0000;
676
  else if (transparent_color_wr) transparent_color <=  gpu_data_i;
677
 
678
assign cfg_transparent_color_o = transparent_color;
679
 
680
endmodule // ogfx_gpu_reg
681
 
682
`ifdef OGFX_NO_INCLUDE
683
`else
684
`include "openGFX430_undefines.v"
685
`endif

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