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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [opengfx430/] [ogfx_reg_vram_if.v] - Blame information for rev 221

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1 221 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2015 Authors
3
//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
8
//
9
// This source file is free software; you can redistribute it and/or modify
10
// it under the terms of the GNU Lesser General Public License as published
11
// by the Free Software Foundation; either version 2.1 of the License, or
12
// (at your option) any later version.
13
//
14
// This source is distributed in the hope that it will be useful, but WITHOUT
15
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
19
// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
22
//
23
//----------------------------------------------------------------------------
24
//
25
// *File Name: ogfx_reg_vram_if.v
26
//
27
// *Module Description:
28
//                      Video-RAM Registers interface.
29
//
30
// *Author(s):
31
//              - Olivier Girard,    olgirard@gmail.com
32
//
33
//----------------------------------------------------------------------------
34
// $Rev$
35
// $LastChangedBy$
36
// $LastChangedDate$
37
//----------------------------------------------------------------------------
38
`ifdef OGFX_NO_INCLUDE
39
`else
40
`include "openGFX430_defines.v"
41
`endif
42
 
43
module  ogfx_reg_vram_if (
44
 
45
// OUTPUTs
46
    vid_ram_cfg_o,                             // VID_RAMx_CFG     Register
47
    vid_ram_width_o,                           // VID_RAMx_WIDTH   Register
48
`ifdef VRAM_BIGGER_4_KW
49
    vid_ram_addr_hi_o,                         // VID_RAMx_ADDR_HI Register
50
`endif
51
    vid_ram_addr_lo_o,                         // VID_RAMx_ADDR_LO Register
52
    vid_ram_data_o,                            // VID_RAMx_DATA    Register
53
 
54
    vid_ram_we_o,                              // Video-RAM Write strobe
55
    vid_ram_ce_o,                              // Video-RAM Chip enable
56
    vid_ram_din_o,                             // Video-RAM Data input
57
    vid_ram_addr_nxt_o,                        // Video-RAM Next address
58
    vid_ram_access_o,                          // Video-RAM Access
59
 
60
// INPUTs
61
    mclk,                                      // Main system clock
62
    puc_rst,                                   // Main system reset
63
 
64
    vid_ram_cfg_wr_i,                          // VID_RAMx_CFG     Write strobe
65
    vid_ram_width_wr_i,                        // VID_RAMx_WIDTH   Write strobe
66
    vid_ram_addr_hi_wr_i,                      // VID_RAMx_ADDR_HI Write strobe
67
    vid_ram_addr_lo_wr_i,                      // VID_RAMx_ADDR_LO Write strobe
68
    vid_ram_data_wr_i,                         // VID_RAMx_DATA    Write strobe
69
    vid_ram_data_rd_i,                         // VID_RAMx_DATA    Read  strobe
70
 
71
    dbg_freeze_i,                              // Freeze auto-increment on read when CPU stopped
72
    display_width_i,                           // Display width
73
    gfx_mode_1_bpp_i,                          // Graphic mode  1 bpp resolution
74
    gfx_mode_2_bpp_i,                          // Graphic mode  2 bpp resolution
75
    gfx_mode_4_bpp_i,                          // Graphic mode  4 bpp resolution
76
    gfx_mode_8_bpp_i,                          // Graphic mode  8 bpp resolution
77
    gfx_mode_16_bpp_i,                         // Graphic mode 16 bpp resolution
78
 
79
    per_din_i,                                 // Peripheral data input
80
    vid_ram_base_addr_i,                       // Video-RAM base address
81
    vid_ram_dout_i                             // Video-RAM data input
82
);
83
 
84
// OUTPUTs
85
//=========
86
output        [15:0] vid_ram_cfg_o;            // VID_RAMx_CFG     Register
87
output        [15:0] vid_ram_width_o;          // VID_RAMx_WIDTH   Register
88
`ifdef VRAM_BIGGER_4_KW
89
output        [15:0] vid_ram_addr_hi_o;        // VID_RAMx_ADDR_HI Register
90
`endif
91
output        [15:0] vid_ram_addr_lo_o;        // VID_RAMx_ADDR_LO Register
92
output        [15:0] vid_ram_data_o;           // VID_RAMx_DATA    Register
93
 
94
output               vid_ram_we_o;             // Video-RAM Write strobe
95
output               vid_ram_ce_o;             // Video-RAM Chip enable
96
output        [15:0] vid_ram_din_o;            // Video-RAM Data input
97
output [`APIX_MSB:0] vid_ram_addr_nxt_o;       // Video-RAM Next address
98
output               vid_ram_access_o;         // Video-RAM Access
99
 
100
// INPUTs
101
//=========
102
input                mclk;                     // Main system clock
103
input                puc_rst;                  // Main system reset
104
 
105
input                vid_ram_cfg_wr_i;         // VID_RAMx_CFG     Write strobe
106
input                vid_ram_width_wr_i;       // VID_RAMx_WIDTH   Write strobe
107
input                vid_ram_addr_hi_wr_i;     // VID_RAMx_ADDR_HI Write strobe
108
input                vid_ram_addr_lo_wr_i;     // VID_RAMx_ADDR_LO Write strobe
109
input                vid_ram_data_wr_i;        // VID_RAMx_DATA    Write strobe
110
input                vid_ram_data_rd_i;        // VID_RAMx_DATA    Read  strobe
111
 
112
input                dbg_freeze_i;             // Freeze auto-increment on read when CPU stopped
113
input  [`LPIX_MSB:0] display_width_i;          // Display width
114
input                gfx_mode_1_bpp_i;         // Graphic mode  1 bpp resolution
115
input                gfx_mode_2_bpp_i;         // Graphic mode  2 bpp resolution
116
input                gfx_mode_4_bpp_i;         // Graphic mode  4 bpp resolution
117
input                gfx_mode_8_bpp_i;         // Graphic mode  8 bpp resolution
118
input                gfx_mode_16_bpp_i;        // Graphic mode 16 bpp resolution
119
 
120
input         [15:0] per_din_i;                // Peripheral data input
121
input  [`APIX_MSB:0] vid_ram_base_addr_i;      // Video-RAM base address
122
input         [15:0] vid_ram_dout_i;           // Video-RAM data input
123
 
124
 
125
//=============================================================================
126
// 1)  WIRE AND FUNCTION DECLARATIONS
127
//=============================================================================
128
 
129
// 16 bits one-hot decoder
130
function [15:0] one_hot16;
131
   input  [3:0] binary;
132
   begin
133
      one_hot16         = 16'h0000;
134
      one_hot16[binary] =  1'b1;
135
   end
136
endfunction
137
 
138
 
139
 
140
//============================================================================
141
// 2) REGISTERS
142
//============================================================================
143
 
144
//------------------------------------------------
145
// VID_RAMx_CFG Register
146
//------------------------------------------------
147
reg                vid_ram_rmw_mode;
148
reg                vid_ram_msk_mode;
149
reg                vid_ram_win_mode;
150
reg                vid_ram_win_x_swap;
151
reg                vid_ram_win_y_swap;
152
reg                vid_ram_win_cl_swap;
153
 
154
always @ (posedge mclk or posedge puc_rst)
155
  if (puc_rst)
156
    begin
157
       vid_ram_win_cl_swap  <=  1'b0;
158
       vid_ram_win_y_swap   <=  1'b0;
159
       vid_ram_win_x_swap   <=  1'b0;
160
       vid_ram_rmw_mode     <=  1'b0;
161
       vid_ram_msk_mode     <=  1'b0;
162
       vid_ram_win_mode     <=  1'b0;
163
    end
164
  else if (vid_ram_cfg_wr_i)
165
    begin
166
       vid_ram_win_cl_swap  <=  per_din_i[0];
167
       vid_ram_win_y_swap   <=  per_din_i[1];
168
       vid_ram_win_x_swap   <=  per_din_i[2];
169
       vid_ram_rmw_mode     <=  per_din_i[4];
170
       vid_ram_msk_mode     <=  per_din_i[5];
171
       vid_ram_win_mode     <=  per_din_i[6];
172
    end
173
 
174
assign vid_ram_cfg_o  = {8'h00, 1'b0,  vid_ram_win_mode,   vid_ram_msk_mode,   vid_ram_rmw_mode   ,
175
                                1'b0,  vid_ram_win_x_swap, vid_ram_win_y_swap, vid_ram_win_cl_swap};
176
 
177
//------------------------------------------------
178
// VID_RAMx_WIDTH Register
179
//------------------------------------------------
180
reg  [`LPIX_MSB:0] vid_ram_width;
181
 
182
// width must be at least 1
183
wire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1'b0}}, 1'b1};
184
 
185
always @ (posedge mclk or posedge puc_rst)
186
  if (puc_rst)                 vid_ram_width   <=  {{`LPIX_MSB{1'b0}}, 1'b1};
187
  else if (vid_ram_width_wr_i) vid_ram_width   <=  vid_ram_width_nxt;
188
 
189
wire [16:0] vid_ram_width_tmp = {{16-`LPIX_MSB{1'b0}}, vid_ram_width};
190
assign      vid_ram_width_o   = vid_ram_width_tmp[15:0];
191
 
192
 
193
//------------------------------------------------
194
// VID_RAMx_ADDR_HI Register
195
//------------------------------------------------
196
wire   [`APIX_MSB:0] vid_ram_addr;
197
wire   [`APIX_MSB:0] vid_ram_addr_inc;
198
wire                 vid_ram_addr_inc_wr;
199
reg                  vid_ram_addr_hi_wr_dly;
200
 
201
`ifdef VRAM_BIGGER_4_KW
202
reg [`APIX_HI_MSB:0] vid_ram_addr_hi;
203
 
204
always @ (posedge mclk or posedge puc_rst)
205
  if (puc_rst)                   vid_ram_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
206
  else if (vid_ram_addr_hi_wr_i) vid_ram_addr_hi <=  per_din_i[`APIX_HI_MSB:0];
207
  else if (vid_ram_addr_inc_wr)  vid_ram_addr_hi <=  vid_ram_addr_inc[`APIX_MSB:16];
208
 
209
wire [16:0] vid_ram_addr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}},vid_ram_addr_hi};
210
assign      vid_ram_addr_hi_o   = vid_ram_addr_hi_tmp[15:0];
211
`endif
212
 
213
//------------------------------------------------
214
// VID_RAMx_ADDR_LO Register
215
//------------------------------------------------
216
reg [`APIX_LO_MSB:0] vid_ram_addr_lo;
217
 
218
always @ (posedge mclk or posedge puc_rst)
219
  if (puc_rst)                   vid_ram_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
220
  else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <=  per_din_i[`APIX_LO_MSB:0];
221
  else if (vid_ram_addr_inc_wr)  vid_ram_addr_lo <=  vid_ram_addr_inc[`APIX_LO_MSB:0];
222
 
223
`ifdef VRAM_BIGGER_4_KW
224
assign      vid_ram_addr        = {vid_ram_addr_hi[`APIX_HI_MSB:0], vid_ram_addr_lo};
225
assign      vid_ram_addr_lo_o   =  vid_ram_addr_lo;
226
`else
227
assign      vid_ram_addr        = {vid_ram_addr_lo[`APIX_LO_MSB:0]};
228
wire [16:0] vid_ram_addr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}},vid_ram_addr_lo};
229
assign      vid_ram_addr_lo_o   = vid_ram_addr_lo_tmp[15:0];
230
`endif
231
 
232
// Compute the next address
233
ogfx_reg_vram_addr ogfx_reg_vram_addr_inst (
234
 
235
// OUTPUTs
236
    .vid_ram_addr_nxt_o      ( vid_ram_addr_inc       ),   // Next Video-RAM address
237
 
238
// INPUTs
239
    .mclk                    ( mclk                   ),   // Main system clock
240
    .puc_rst                 ( puc_rst                ),   // Main system reset
241
    .display_width_i         ( display_width_i        ),   // Display width
242
    .gfx_mode_1_bpp_i        ( gfx_mode_1_bpp_i       ),   // Graphic mode  1 bpp resolution
243
    .gfx_mode_2_bpp_i        ( gfx_mode_2_bpp_i       ),   // Graphic mode  2 bpp resolution
244
    .gfx_mode_4_bpp_i        ( gfx_mode_4_bpp_i       ),   // Graphic mode  4 bpp resolution
245
    .gfx_mode_8_bpp_i        ( gfx_mode_8_bpp_i       ),   // Graphic mode  8 bpp resolution
246
    .gfx_mode_16_bpp_i       ( gfx_mode_16_bpp_i      ),   // Graphic mode 16 bpp resolution
247
    .vid_ram_addr_i          ( vid_ram_addr           ),   // Video-RAM address
248
    .vid_ram_addr_init_i     ( vid_ram_addr_hi_wr_dly ),   // Video-RAM address initialization
249
    .vid_ram_addr_step_i     ( vid_ram_addr_inc_wr    ),   // Video-RAM address step
250
    .vid_ram_width_i         ( vid_ram_width          ),   // Video-RAM width
251
    .vid_ram_msk_mode_i      ( vid_ram_msk_mode       ),   // Video-RAM Mask mode enable
252
    .vid_ram_win_mode_i      ( vid_ram_win_mode       ),   // Video-RAM Windows mode enable
253
    .vid_ram_win_x_swap_i    ( vid_ram_win_x_swap     ),   // Video-RAM X-Swap configuration
254
    .vid_ram_win_y_swap_i    ( vid_ram_win_y_swap     ),   // Video-RAM Y-Swap configuration
255
    .vid_ram_win_cl_swap_i   ( vid_ram_win_cl_swap    )    // Video-RAM CL-Swap configuration
256
);
257
 
258
 
259
//------------------------------------------------
260
// VID_RAMx_DATA Register
261
//------------------------------------------------
262
 
263
// Format input data for masked mode
264
wire [15:0] per_din_mask_mode = (({16{gfx_mode_1_bpp_i  &  vid_ram_msk_mode }} & {16{per_din_i[0]  }}) |
265
                                 ({16{gfx_mode_2_bpp_i  &  vid_ram_msk_mode }} &  {8{per_din_i[1:0]}}) |
266
                                 ({16{gfx_mode_4_bpp_i  &  vid_ram_msk_mode }} &  {4{per_din_i[3:0]}}) |
267
                                 ({16{gfx_mode_8_bpp_i  &  vid_ram_msk_mode }} &  {2{per_din_i[7:0]}}) |
268
                                 ({16{gfx_mode_16_bpp_i | ~vid_ram_msk_mode }} &     per_din_i       ) );
269
 
270
// Prepare data to be written according to mask mode enable
271
reg  [15:0] vid_ram_data_mask;
272
wire [15:0] per_din_ram_nxt   = per_din_mask_mode & vid_ram_data_mask;
273
 
274
// VIDEO-RAM data Register
275
reg  [15:0] vid_ram_data;
276
wire [15:0] vid_ram_data_mux;
277
wire        vid_ram_dout_rdy;
278
always @ (posedge mclk or posedge puc_rst)
279
  if (puc_rst)                vid_ram_data <=  16'h0000;
280
  else if (vid_ram_data_wr_i) vid_ram_data <=  per_din_ram_nxt | (vid_ram_data_mux & ~vid_ram_data_mask);
281
  else if (vid_ram_dout_rdy)  vid_ram_data <=  vid_ram_dout_i;
282
 
283
// Make value available in case of early read
284
assign      vid_ram_data_mux            =  vid_ram_dout_rdy ? vid_ram_dout_i : vid_ram_data;
285
 
286
// Format read-path for mask mode
287
wire [15:0] vid_ram_data_rd_mask        =  vid_ram_data_mux & vid_ram_data_mask;
288
wire        vid_ram_data_rd_mask_1_bpp  =  (|vid_ram_data_rd_mask);
289
wire  [1:0] vid_ram_data_rd_mask_2_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[9], vid_ram_data_rd_mask[7], vid_ram_data_rd_mask[5], vid_ram_data_rd_mask[3], vid_ram_data_rd_mask[1]}),
290
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[8], vid_ram_data_rd_mask[6], vid_ram_data_rd_mask[4], vid_ram_data_rd_mask[2], vid_ram_data_rd_mask[0]})};
291
wire  [3:0] vid_ram_data_rd_mask_4_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[7] , vid_ram_data_rd_mask[3]}),
292
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[6] , vid_ram_data_rd_mask[2]}),
293
                                           (|{vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[9] , vid_ram_data_rd_mask[5] , vid_ram_data_rd_mask[1]}),
294
                                           (|{vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[8] , vid_ram_data_rd_mask[4] , vid_ram_data_rd_mask[0]})};
295
wire  [7:0] vid_ram_data_rd_mask_8_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[7]}),
296
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[6]}),
297
                                           (|{vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[5]}),
298
                                           (|{vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[4]}),
299
                                           (|{vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[3]}),
300
                                           (|{vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[2]}),
301
                                           (|{vid_ram_data_rd_mask[9] , vid_ram_data_rd_mask[1]}),
302
                                           (|{vid_ram_data_rd_mask[8] , vid_ram_data_rd_mask[0]})};
303
wire [15:0] vid_ram_data_rd_mask_16_bpp =     vid_ram_data_rd_mask;
304
 
305
assign      vid_ram_data_o              =  ({16{gfx_mode_1_bpp_i  &  vid_ram_msk_mode }} & {{15{1'b0}},vid_ram_data_rd_mask_1_bpp}) |
306
                                           ({16{gfx_mode_2_bpp_i  &  vid_ram_msk_mode }} & {{14{1'b0}},vid_ram_data_rd_mask_2_bpp}) |
307
                                           ({16{gfx_mode_4_bpp_i  &  vid_ram_msk_mode }} & {{12{1'b0}},vid_ram_data_rd_mask_4_bpp}) |
308
                                           ({16{gfx_mode_8_bpp_i  &  vid_ram_msk_mode }} & { {8{1'b0}},vid_ram_data_rd_mask_8_bpp}) |
309
                                           ({16{gfx_mode_16_bpp_i | ~vid_ram_msk_mode }} &             vid_ram_data_rd_mask_16_bpp) ;
310
 
311
 
312
//============================================================================
313
// 3) VIDEO MEMORY INTERFACE
314
//============================================================================
315
//
316
// Trigger a VIDEO-RAM write access after:
317
//   - a VID_RAMx_DATA register write access
318
//
319
// Trigger a VIDEO-RAM read access immediately after:
320
//   - a VID_RAMx_ADDR_LO register write access
321
//   - a VID_RAMx_DATA register read access
322
//   - a VID_RAMx_DATA register write access in MSK mode (for resolutions lower than 16bpp)
323
//
324
 
325
//--------------------------------------------------
326
// VID_RAM0: Delay software read and write strobes
327
//--------------------------------------------------
328
 
329
// Strobe writing to VID_RAMx_ADDR_LO register
330
always @ (posedge mclk or posedge puc_rst)
331
  if (puc_rst) vid_ram_addr_hi_wr_dly  <= 1'b0;
332
  else         vid_ram_addr_hi_wr_dly  <= vid_ram_addr_hi_wr_i;
333
 
334
// Strobe reading from VID_RAMx_DATA register
335
reg        vid_ram_data_rd_dly;
336
always @ (posedge mclk or posedge puc_rst)
337
  if (puc_rst) vid_ram_data_rd_dly     <= 1'b0;
338
  else         vid_ram_data_rd_dly     <= vid_ram_data_rd_i;
339
 
340
// Strobe writing to VID_RAMx_DATA register
341
reg        vid_ram_data_wr_dly;
342
always @ (posedge mclk or posedge puc_rst)
343
  if (puc_rst) vid_ram_data_wr_dly     <= 1'b0;
344
  else         vid_ram_data_wr_dly     <= vid_ram_data_wr_i;
345
 
346
// Trigger read access after a write in MSK mode
347
wire       vid_ram_data_rd_msk   = ((vid_ram_data_wr_dly  | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i) & vid_ram_msk_mode & ~gfx_mode_16_bpp_i);
348
 
349
 
350
//------------------------------------------------
351
// Compute VIDEO-RAM Strobes & Data
352
//------------------------------------------------
353
 
354
// Write access strobe
355
//       - one cycle after a VID_RAM_DATA register write access
356
assign vid_ram_we_o     =  vid_ram_data_wr_dly;
357
 
358
// Chip enable.
359
// Note: we perform a data read access:
360
//       - one cycle after a VID_RAM_DATA register read access (so that the address has been incremented)
361
//       - one cycle after a VID_RAM_ADDR_LO register write
362
wire   vid_ram_ce_early = (vid_ram_addr_hi_wr_i | vid_ram_data_rd_dly | vid_ram_data_rd_msk | // Read access
363
                           vid_ram_data_wr_i);                                                // Write access
364
 
365
reg [1:0] vid_ram_ce;
366
always @ (posedge mclk or posedge puc_rst)
367
  if (puc_rst) vid_ram_ce <= 2'b00;
368
  else         vid_ram_ce <= {vid_ram_ce[0] & ~vid_ram_data_wr_dly, vid_ram_ce_early};
369
 
370
assign vid_ram_ce_o     = vid_ram_ce[0];
371
 
372
// Data to be written
373
assign vid_ram_din_o    = {16{vid_ram_ce[0]}} & vid_ram_data;
374
 
375
// Update the VRAM_DATA register one cycle after each memory access
376
assign vid_ram_dout_rdy = vid_ram_ce[1];
377
 
378
 
379
//------------------------------------------------
380
// Compute VIDEO-RAM Address
381
//------------------------------------------------
382
 
383
// Mux ram address for early read access when ADDR_LO is updated
384
`ifdef VRAM_BIGGER_4_KW
385
wire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_HI_MSB:0], vid_ram_addr[15:0]} :
386
                                         vid_ram_data_rd_msk  ?  vid_ram_addr_inc                               : vid_ram_addr;
387
`else
388
wire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :
389
                                         vid_ram_data_rd_msk  ?  vid_ram_addr_inc                               : vid_ram_addr;
390
`endif
391
 
392
// Add frame pointer offset
393
wire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;
394
 
395
// Detect memory accesses for ADDR update
396
wire               vid_ram_access_o    = vid_ram_data_wr_i | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i | vid_ram_data_rd_msk;
397
 
398
// Mux Address between the two interfaces
399
wire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;
400
 
401
// Increment the address when accessing the VID_RAMx_DATA register:
402
// - one clock cycle after a write access
403
// - with the read access (if not in read-modify-write mode)
404
assign             vid_ram_addr_inc_wr = vid_ram_addr_hi_wr_dly | vid_ram_data_wr_dly | (vid_ram_data_rd_i & ~dbg_freeze_i & ~vid_ram_rmw_mode);
405
 
406
// Compute mask for the address LSBs depending on BPP resolution
407
wire         [3:0] gfx_mode_addr_msk   = (        {4{gfx_mode_1_bpp_i}}  | // Take  4 address LSBs in  1bpp mode
408
                                          {1'b0,  {3{gfx_mode_2_bpp_i}}} | // Take  3 address LSBs in  2bpp mode
409
                                          {2'b00, {2{gfx_mode_4_bpp_i}}} | // Take  2 address LSBs in  4bpp mode
410
                                          {3'b000,   gfx_mode_8_bpp_i});   // Take  1 address LSB  in  8bpp mode
411
                                                                           // Take no address LSB  in 16bpp mode
412
// Generate Data-Mask for the mask mode (Bank 0)
413
wire    [15:0] vid_ram_data_mask_shift = one_hot16(vid_ram_addr_offset[3:0] & gfx_mode_addr_msk);
414
wire    [15:0] vid_ram_data_mask_nxt   = ({16{gfx_mode_1_bpp_i }} &     vid_ram_data_mask_shift      ) |
415
                                         ({16{gfx_mode_2_bpp_i }} & {{2{vid_ram_data_mask_shift[7]}},
416
                                                                     {2{vid_ram_data_mask_shift[6]}},
417
                                                                     {2{vid_ram_data_mask_shift[5]}},
418
                                                                     {2{vid_ram_data_mask_shift[4]}},
419
                                                                     {2{vid_ram_data_mask_shift[3]}},
420
                                                                     {2{vid_ram_data_mask_shift[2]}},
421
                                                                     {2{vid_ram_data_mask_shift[1]}},
422
                                                                     {2{vid_ram_data_mask_shift[0]}}}) |
423
                                         ({16{gfx_mode_4_bpp_i }} & {{4{vid_ram_data_mask_shift[3]}},
424
                                                                     {4{vid_ram_data_mask_shift[2]}},
425
                                                                     {4{vid_ram_data_mask_shift[1]}},
426
                                                                     {4{vid_ram_data_mask_shift[0]}}}) |
427
                                         ({16{gfx_mode_8_bpp_i }} & {{8{vid_ram_data_mask_shift[1]}},
428
                                                                     {8{vid_ram_data_mask_shift[0]}}}) |
429
                                         ({16{gfx_mode_16_bpp_i}} & {16{1'b1}}                       ) ;
430
 
431
always @ (posedge mclk or posedge puc_rst)
432
  if (puc_rst)                   vid_ram_data_mask <=  16'hffff;
433
  else if (vid_ram_data_rd_msk)  vid_ram_data_mask <=  vid_ram_data_mask_nxt;
434
  else if (vid_ram_access_o)     vid_ram_data_mask <=  16'hffff;
435
 
436
 
437
endmodule // ogfx_reg_vram_if
438
 
439
`ifdef OGFX_NO_INCLUDE
440
`else
441
`include "openGFX430_undefines.v"
442
`endif

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