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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2016 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openGFX430.v
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//
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// *Module Description:
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// This is a basic video controller for the openMSP430.
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//
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// It is currently supporting the LT24 LCD Board but
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// can be extended to anything.
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module openGFX430 (
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// OUTPUTs
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irq_gfx_o, // Graphic Controller interrupt
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lt24_cs_n_o, // LT24 Chip select (Active low)
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lt24_rd_n_o, // LT24 Read strobe (Active low)
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lt24_wr_n_o, // LT24 Write strobe (Active low)
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lt24_rs_o, // LT24 Command/Param selection (Cmd=0/Param=1)
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lt24_d_o, // LT24 Data output
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lt24_d_en_o, // LT24 Data output enable
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lt24_reset_n_o, // LT24 Reset (Active Low)
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lt24_on_o, // LT24 on/off
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per_dout_o, // Peripheral data output
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_addr_o, // LUT-RAM address
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lut_ram_wen_o, // LUT-RAM write enable (active low)
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lut_ram_cen_o, // LUT-RAM enable (active low)
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lut_ram_din_o, // LUT-RAM data input
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`endif
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vid_ram_addr_o, // Video-RAM address
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vid_ram_wen_o, // Video-RAM write enable (active low)
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vid_ram_cen_o, // Video-RAM enable (active low)
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vid_ram_din_o, // Video-RAM data input
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// INPUTs
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dbg_freeze_i, // Freeze address auto-incr on read
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mclk, // Main system clock
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per_addr_i, // Peripheral address
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per_din_i, // Peripheral data input
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per_en_i, // Peripheral enable (high active)
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per_we_i, // Peripheral write enable (high active)
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puc_rst, // Main system reset
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lt24_d_i, // LT24 Data input
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_dout_i, // LUT-RAM data output
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`endif
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vid_ram_dout_i // Video-RAM data output
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);
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// OUTPUTs
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//=========
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output irq_gfx_o; // Graphic Controller interrupt
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output lt24_cs_n_o; // LT24 Chip select (Active low)
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output lt24_rd_n_o; // LT24 Read strobe (Active low)
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output lt24_wr_n_o; // LT24 Write strobe (Active low)
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output lt24_rs_o; // LT24 Command/Param selection (Cmd=0/Param=1)
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output [15:0] lt24_d_o; // LT24 Data output
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output lt24_d_en_o; // LT24 Data output enable
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output lt24_reset_n_o; // LT24 Reset (Active Low)
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output lt24_on_o; // LT24 on/off
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output [15:0] per_dout_o; // Peripheral data output
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`ifdef WITH_PROGRAMMABLE_LUT
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output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
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output lut_ram_wen_o; // LUT-RAM write enable (active low)
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output lut_ram_cen_o; // LUT-RAM enable (active low)
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output [15:0] lut_ram_din_o; // LUT-RAM data input
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`endif
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output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
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output vid_ram_wen_o; // Video-RAM write enable (active low)
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output vid_ram_cen_o; // Video-RAM enable (active low)
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output [15:0] vid_ram_din_o; // Video-RAM data input
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// INPUTs
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//=========
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input dbg_freeze_i; // Freeze address auto-incr on read
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input mclk; // Main system clock
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input [13:0] per_addr_i; // Peripheral address
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input [15:0] per_din_i; // Peripheral data input
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input per_en_i; // Peripheral enable (high active)
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input [1:0] per_we_i; // Peripheral write enable (high active)
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input puc_rst; // Main system reset
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input [15:0] lt24_d_i; // LT24 Data input
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`ifdef WITH_PROGRAMMABLE_LUT
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input [15:0] lut_ram_dout_i; // LUT-RAM data output
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`endif
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input [15:0] vid_ram_dout_i; // Video-RAM data output
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//=============================================================================
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// 1) WIRE & PARAMETER DECLARATION
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//=============================================================================
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wire [2:0] lt24_cfg_clk;
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wire [11:0] lt24_cfg_refr;
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wire lt24_cfg_refr_sync_en;
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wire [9:0] lt24_cfg_refr_sync_val;
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wire lt24_cmd_refr;
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wire [7:0] lt24_cmd_val;
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wire lt24_cmd_has_param;
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wire [15:0] lt24_cmd_param;
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wire lt24_cmd_param_rdy;
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wire [15:0] lt24_cmd_dfill;
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wire lt24_cmd_dfill_wr;
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wire [`LPIX_MSB:0] display_width;
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wire [`LPIX_MSB:0] display_height;
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wire [`SPIX_MSB:0] display_size;
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wire display_y_swap;
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wire display_x_swap;
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wire display_cl_swap;
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wire [2:0] gfx_mode;
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wire [4:0] lt24_status;
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wire lt24_done_evt;
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wire lt24_start_evt;
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`ifdef WITH_PROGRAMMABLE_LUT
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wire [`LRAM_MSB:0] lut_ram_sw_addr;
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wire [15:0] lut_ram_sw_din;
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wire lut_ram_sw_wen;
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wire lut_ram_sw_cen;
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wire [15:0] lut_ram_sw_dout;
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wire [`LRAM_MSB:0] lut_ram_refr_addr;
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wire lut_ram_refr_cen;
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wire [15:0] lut_ram_refr_dout;
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wire lut_ram_refr_dout_rdy_nxt;
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`endif
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wire [`VRAM_MSB:0] vid_ram_sw_addr;
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wire [15:0] vid_ram_sw_din;
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wire vid_ram_sw_wen;
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wire vid_ram_sw_cen;
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wire [15:0] vid_ram_sw_dout;
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wire [`VRAM_MSB:0] vid_ram_gpu_addr;
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wire [15:0] vid_ram_gpu_din;
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wire vid_ram_gpu_wen;
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wire vid_ram_gpu_cen;
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wire [15:0] vid_ram_gpu_dout;
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wire vid_ram_gpu_dout_rdy_nxt;
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wire [`VRAM_MSB:0] vid_ram_refr_addr;
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wire vid_ram_refr_cen;
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wire [15:0] vid_ram_refr_dout;
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wire vid_ram_refr_dout_rdy_nxt;
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wire refresh_active;
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wire [15:0] refresh_data;
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wire refresh_data_ready;
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wire refresh_data_request;
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wire [`APIX_MSB:0] refresh_frame_addr;
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wire [1:0] refresh_lut_select;
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wire gpu_cmd_done_evt;
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wire gpu_cmd_error_evt;
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wire gpu_dma_busy;
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wire gpu_get_data;
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wire [15:0] gpu_data;
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wire gpu_data_avail;
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wire gpu_enable;
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//============================================================================
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// 2) REGISTERS
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//============================================================================
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ogfx_reg ogfx_reg_inst (
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// OUTPUTs
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.irq_gfx_o ( irq_gfx_o ), // Graphic Controller interrupt
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.gpu_data_o ( gpu_data ), // GPU data
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.gpu_data_avail_o ( gpu_data_avail ), // GPU data available
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.gpu_enable_o ( gpu_enable ), // GPU enable
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.lt24_reset_n_o ( lt24_reset_n_o ), // LT24 Reset (Active Low)
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.lt24_on_o ( lt24_on_o ), // LT24 on/off
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.lt24_cfg_clk_o ( lt24_cfg_clk ), // LT24 Interface clock configuration
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.lt24_cfg_refr_o ( lt24_cfg_refr ), // LT24 Interface refresh configuration
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.lt24_cfg_refr_sync_en_o ( lt24_cfg_refr_sync_en ), // LT24 Interface refresh sync enable configuration
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.lt24_cfg_refr_sync_val_o ( lt24_cfg_refr_sync_val ), // LT24 Interface refresh sync value configuration
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.lt24_cmd_refr_o ( lt24_cmd_refr ), // LT24 Interface refresh command
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.lt24_cmd_val_o ( lt24_cmd_val ), // LT24 Generic command value
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.lt24_cmd_has_param_o ( lt24_cmd_has_param ), // LT24 Generic command has parameters
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.lt24_cmd_param_o ( lt24_cmd_param ), // LT24 Generic command parameter value
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.lt24_cmd_param_rdy_o ( lt24_cmd_param_rdy ), // LT24 Generic command trigger
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.lt24_cmd_dfill_o ( lt24_cmd_dfill ), // LT24 Data fill value
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.lt24_cmd_dfill_wr_o ( lt24_cmd_dfill_wr ), // LT24 Data fill trigger
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.display_width_o ( display_width ), // Display width
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.display_height_o ( display_height ), // Display height
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.display_size_o ( display_size ), // Display size (number of pixels)
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.display_y_swap_o ( display_y_swap ), // Display configuration: swap Y axis (horizontal symmetry)
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.display_x_swap_o ( display_x_swap ), // Display configuration: swap X axis (vertical symmetry)
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.display_cl_swap_o ( display_cl_swap ), // Display configuration: swap column/lines
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.gfx_mode_o ( gfx_mode ), // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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.per_dout_o ( per_dout_o ), // Peripheral data output
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.refresh_frame_addr_o ( refresh_frame_addr ), // Refresh frame base address
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.refresh_lut_select_o ( refresh_lut_select ), // Refresh LUT bank selection
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`ifdef WITH_PROGRAMMABLE_LUT
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.lut_ram_addr_o ( lut_ram_sw_addr ), // LUT-RAM address
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.lut_ram_din_o ( lut_ram_sw_din ), // LUT-RAM data
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.lut_ram_wen_o ( lut_ram_sw_wen ), // LUT-RAM write strobe (active low)
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.lut_ram_cen_o ( lut_ram_sw_cen ), // LUT-RAM chip enable (active low)
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`endif
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.vid_ram_addr_o ( vid_ram_sw_addr ), // Video-RAM address
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.vid_ram_din_o ( vid_ram_sw_din ), // Video-RAM data
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.vid_ram_wen_o ( vid_ram_sw_wen ), // Video-RAM write strobe (active low)
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.vid_ram_cen_o ( vid_ram_sw_cen ), // Video-RAM chip enable (active low)
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// INPUTs
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.dbg_freeze_i ( dbg_freeze_i ), // Freeze address auto-incr on read
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.gpu_cmd_done_evt_i ( gpu_cmd_done_evt ), // GPU command done event
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.gpu_cmd_error_evt_i ( gpu_cmd_error_evt ), // GPU command error event
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.gpu_dma_busy_i ( gpu_dma_busy ), // GPU DMA execution on going
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.gpu_get_data_i ( gpu_get_data ), // GPU get next data
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.lt24_status_i ( lt24_status ), // LT24 FSM Status
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.lt24_start_evt_i ( lt24_start_evt ), // LT24 FSM start event
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.lt24_done_evt_i ( lt24_done_evt ), // LT24 FSM done event
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.mclk ( mclk ), // Main system clock
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.per_addr_i ( per_addr_i ), // Peripheral address
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.per_din_i ( per_din_i ), // Peripheral data input
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.per_en_i ( per_en_i ), // Peripheral enable (high active)
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.per_we_i ( per_we_i ), // Peripheral write enable (high active)
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.puc_rst ( puc_rst ), // Main system reset
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`ifdef WITH_PROGRAMMABLE_LUT
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.lut_ram_dout_i ( lut_ram_sw_dout ), // LUT-RAM data input
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`endif
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.vid_ram_dout_i ( vid_ram_sw_dout ) // Video-RAM data input
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);
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//============================================================================
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// 3) GPU
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//============================================================================
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ogfx_gpu ogfx_gpu_inst (
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// OUTPUTs
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.gpu_cmd_done_evt_o ( gpu_cmd_done_evt ), // GPU command done event
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.gpu_cmd_error_evt_o ( gpu_cmd_error_evt ), // GPU command error event
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.gpu_dma_busy_o ( gpu_dma_busy ), // GPU DMA execution on going
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.gpu_get_data_o ( gpu_get_data ), // GPU get next data
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.vid_ram_addr_o ( vid_ram_gpu_addr ), // Video-RAM address
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.vid_ram_din_o ( vid_ram_gpu_din ), // Video-RAM data
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.vid_ram_wen_o ( vid_ram_gpu_wen ), // Video-RAM write strobe (active low)
|
| 298 |
|
|
.vid_ram_cen_o ( vid_ram_gpu_cen ), // Video-RAM chip enable (active low)
|
| 299 |
|
|
|
| 300 |
|
|
// INPUTs
|
| 301 |
|
|
.mclk ( mclk ), // Main system clock
|
| 302 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
| 303 |
|
|
|
| 304 |
|
|
.display_width_i ( display_width ), // Display width
|
| 305 |
|
|
|
| 306 |
|
|
.gfx_mode_i ( gfx_mode ), // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
|
| 307 |
|
|
|
| 308 |
|
|
.gpu_data_i ( gpu_data ), // GPU data
|
| 309 |
|
|
.gpu_data_avail_i ( gpu_data_avail ), // GPU data available
|
| 310 |
|
|
.gpu_enable_i ( gpu_enable ), // GPU enable
|
| 311 |
|
|
|
| 312 |
|
|
.vid_ram_dout_i ( vid_ram_gpu_dout ), // Video-RAM data input
|
| 313 |
|
|
.vid_ram_dout_rdy_nxt_i ( vid_ram_gpu_dout_rdy_nxt ) // Video-RAM data output ready during next cycle
|
| 314 |
|
|
);
|
| 315 |
|
|
|
| 316 |
|
|
|
| 317 |
|
|
//============================================================================
|
| 318 |
|
|
// 4) LT24 INTERFACE
|
| 319 |
|
|
//============================================================================
|
| 320 |
|
|
|
| 321 |
|
|
ogfx_if_lt24 ogfx_if_lt24_inst (
|
| 322 |
|
|
|
| 323 |
|
|
// OUTPUTs
|
| 324 |
|
|
.event_fsm_done_o ( lt24_done_evt ), // LT24 FSM done event
|
| 325 |
|
|
.event_fsm_start_o ( lt24_start_evt ), // LT24 FSM start event
|
| 326 |
|
|
|
| 327 |
|
|
.lt24_cs_n_o ( lt24_cs_n_o ), // LT24 Chip select (Active low)
|
| 328 |
|
|
.lt24_d_o ( lt24_d_o ), // LT24 Data output
|
| 329 |
|
|
.lt24_d_en_o ( lt24_d_en_o ), // LT24 Data output enable
|
| 330 |
|
|
.lt24_rd_n_o ( lt24_rd_n_o ), // LT24 Read strobe (Active low)
|
| 331 |
|
|
.lt24_rs_o ( lt24_rs_o ), // LT24 Command/Param selection (Cmd=0/Param=1)
|
| 332 |
|
|
.lt24_wr_n_o ( lt24_wr_n_o ), // LT24 Write strobe (Active low)
|
| 333 |
|
|
|
| 334 |
|
|
.refresh_active_o ( refresh_active ), // Display refresh on going
|
| 335 |
|
|
.refresh_data_request_o ( refresh_data_request ), // Display refresh new data request
|
| 336 |
|
|
|
| 337 |
|
|
.status_o ( lt24_status ), // LT24 FSM Status
|
| 338 |
|
|
|
| 339 |
|
|
// INPUTs
|
| 340 |
|
|
.mclk ( mclk ), // Main system clock
|
| 341 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
| 342 |
|
|
|
| 343 |
|
|
.cfg_lt24_clk_div_i ( lt24_cfg_clk ), // Clock Divider configuration for LT24 interface
|
| 344 |
|
|
.cfg_lt24_display_size_i ( display_size ), // Display size (number of pixels)
|
| 345 |
|
|
.cfg_lt24_refresh_i ( lt24_cfg_refr ), // Refresh rate configuration for LT24 interface
|
| 346 |
|
|
.cfg_lt24_refresh_sync_en_i ( lt24_cfg_refr_sync_en ), // Refresh sync enable configuration for LT24 interface
|
| 347 |
|
|
.cfg_lt24_refresh_sync_val_i ( lt24_cfg_refr_sync_val ), // Refresh sync value configuration for LT24 interface
|
| 348 |
|
|
|
| 349 |
|
|
.cmd_dfill_i ( lt24_cmd_dfill ), // Display data fill
|
| 350 |
|
|
.cmd_dfill_trig_i ( lt24_cmd_dfill_wr ), // Trigger a full display data fill
|
| 351 |
|
|
|
| 352 |
|
|
.cmd_generic_cmd_val_i ( lt24_cmd_val ), // Generic command value
|
| 353 |
|
|
.cmd_generic_has_param_i ( lt24_cmd_has_param ), // Generic command to be sent has parameter(s)
|
| 354 |
|
|
.cmd_generic_param_val_i ( lt24_cmd_param ), // Generic command parameter value
|
| 355 |
|
|
.cmd_generic_trig_i ( lt24_cmd_param_rdy ), // Trigger generic command transmit (or new parameter available)
|
| 356 |
|
|
|
| 357 |
|
|
.cmd_refresh_i ( lt24_cmd_refr ), // Display refresh command
|
| 358 |
|
|
|
| 359 |
|
|
.lt24_d_i ( lt24_d_i ), // LT24 Data input
|
| 360 |
|
|
|
| 361 |
|
|
.refresh_data_i ( refresh_data ), // Display refresh data
|
| 362 |
|
|
.refresh_data_ready_i ( refresh_data_ready ) // Display refresh new data is ready
|
| 363 |
|
|
);
|
| 364 |
|
|
|
| 365 |
|
|
//============================================================================
|
| 366 |
|
|
// 5) VIDEO BACKEND
|
| 367 |
|
|
//============================================================================
|
| 368 |
|
|
|
| 369 |
|
|
// Video Backend
|
| 370 |
|
|
ogfx_backend ogfx_backend_inst (
|
| 371 |
|
|
|
| 372 |
|
|
// OUTPUTs
|
| 373 |
|
|
.refresh_data_o ( refresh_data ), // Display refresh data
|
| 374 |
|
|
.refresh_data_ready_o ( refresh_data_ready ), // Display refresh new data is ready
|
| 375 |
|
|
|
| 376 |
|
|
.vid_ram_addr_o ( vid_ram_refr_addr ), // Video-RAM address
|
| 377 |
|
|
.vid_ram_cen_o ( vid_ram_refr_cen ), // Video-RAM enable (active low)
|
| 378 |
|
|
|
| 379 |
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
| 380 |
|
|
.lut_ram_addr_o ( lut_ram_refr_addr ), // LUT-RAM address
|
| 381 |
|
|
.lut_ram_cen_o ( lut_ram_refr_cen ), // LUT-RAM enable (active low)
|
| 382 |
|
|
`endif
|
| 383 |
|
|
|
| 384 |
|
|
// INPUTs
|
| 385 |
|
|
.mclk ( mclk ), // Main system clock
|
| 386 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
| 387 |
|
|
|
| 388 |
|
|
.display_width_i ( display_width ), // Display width
|
| 389 |
|
|
.display_height_i ( display_height ), // Display height
|
| 390 |
|
|
.display_size_i ( display_size ), // Display size (number of pixels)
|
| 391 |
|
|
.display_y_swap_i ( display_y_swap ), // Display configuration: swap Y axis (horizontal symmetry)
|
| 392 |
|
|
.display_x_swap_i ( display_x_swap ), // Display configuration: swap X axis (vertical symmetry)
|
| 393 |
|
|
.display_cl_swap_i ( display_cl_swap ), // Display configuration: swap column/lines
|
| 394 |
|
|
|
| 395 |
|
|
.gfx_mode_i ( gfx_mode ), // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
|
| 396 |
|
|
|
| 397 |
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
| 398 |
|
|
.lut_ram_dout_i ( lut_ram_refr_dout ), // LUT-RAM data output
|
| 399 |
|
|
.lut_ram_dout_rdy_nxt_i ( lut_ram_refr_dout_rdy_nxt ), // LUT-RAM data output ready during next cycle
|
| 400 |
|
|
`endif
|
| 401 |
|
|
|
| 402 |
|
|
.vid_ram_dout_i ( vid_ram_refr_dout ), // Video-RAM data output
|
| 403 |
|
|
.vid_ram_dout_rdy_nxt_i ( vid_ram_refr_dout_rdy_nxt ), // Video-RAM data output ready during next cycle
|
| 404 |
|
|
|
| 405 |
|
|
.refresh_active_i ( refresh_active ), // Display refresh on going
|
| 406 |
|
|
.refresh_data_request_i ( refresh_data_request ), // Display refresh new data request
|
| 407 |
|
|
.refresh_frame_base_addr_i ( refresh_frame_addr ), // Refresh frame base address
|
| 408 |
|
|
.refresh_lut_select_i ( refresh_lut_select ) // Refresh LUT bank selection
|
| 409 |
|
|
);
|
| 410 |
|
|
|
| 411 |
|
|
//============================================================================
|
| 412 |
|
|
// 6) ARBITER FOR VIDEO AND LUT MEMORIES
|
| 413 |
|
|
//============================================================================
|
| 414 |
|
|
|
| 415 |
|
|
ogfx_ram_arbiter ogfx_ram_arbiter_inst (
|
| 416 |
|
|
|
| 417 |
|
|
.mclk ( mclk ), // Main system clock
|
| 418 |
|
|
.puc_rst ( puc_rst ), // Main system reset
|
| 419 |
|
|
|
| 420 |
|
|
//------------------------------------------------------------
|
| 421 |
|
|
|
| 422 |
|
|
// SW interface, fixed highest priority
|
| 423 |
|
|
.lut_ram_sw_addr_i ( lut_ram_sw_addr ), // LUT-RAM Software address
|
| 424 |
|
|
.lut_ram_sw_din_i ( lut_ram_sw_din ), // LUT-RAM Software data
|
| 425 |
|
|
.lut_ram_sw_wen_i ( lut_ram_sw_wen ), // LUT-RAM Software write strobe (active low)
|
| 426 |
|
|
.lut_ram_sw_cen_i ( lut_ram_sw_cen ), // LUT-RAM Software chip enable (active low)
|
| 427 |
|
|
.lut_ram_sw_dout_o ( lut_ram_sw_dout ), // LUT-RAM Software data input
|
| 428 |
|
|
|
| 429 |
|
|
// Refresh-backend, fixed lowest priority
|
| 430 |
|
|
.lut_ram_refr_addr_i ( lut_ram_refr_addr ), // LUT-RAM Refresh address
|
| 431 |
|
|
.lut_ram_refr_din_i ( 16'h0000 ), // LUT-RAM Refresh data
|
| 432 |
|
|
.lut_ram_refr_wen_i ( 1'h1 ), // LUT-RAM Refresh write strobe (active low)
|
| 433 |
|
|
.lut_ram_refr_cen_i ( lut_ram_refr_cen ), // LUT-RAM Refresh enable (active low)
|
| 434 |
|
|
.lut_ram_refr_dout_o ( lut_ram_refr_dout ), // LUT-RAM Refresh data output
|
| 435 |
|
|
.lut_ram_refr_dout_rdy_nxt_o ( lut_ram_refr_dout_rdy_nxt ), // LUT-RAM Refresh data output ready during next cycle
|
| 436 |
|
|
|
| 437 |
|
|
// LUT Memory interface
|
| 438 |
|
|
.lut_ram_addr_o ( lut_ram_addr_o ), // LUT-RAM address
|
| 439 |
|
|
.lut_ram_din_o ( lut_ram_din_o ), // LUT-RAM data
|
| 440 |
|
|
.lut_ram_wen_o ( lut_ram_wen_o ), // LUT-RAM write strobe (active low)
|
| 441 |
|
|
.lut_ram_cen_o ( lut_ram_cen_o ), // LUT-RAM chip enable (active low)
|
| 442 |
|
|
.lut_ram_dout_i ( lut_ram_dout_i ), // LUT-RAM data input
|
| 443 |
|
|
|
| 444 |
|
|
//------------------------------------------------------------
|
| 445 |
|
|
|
| 446 |
|
|
// SW interface, fixed highest priority
|
| 447 |
|
|
.vid_ram_sw_addr_i ( vid_ram_sw_addr ), // Video-RAM Software address
|
| 448 |
|
|
.vid_ram_sw_din_i ( vid_ram_sw_din ), // Video-RAM Software data
|
| 449 |
|
|
.vid_ram_sw_wen_i ( vid_ram_sw_wen ), // Video-RAM Software write strobe (active low)
|
| 450 |
|
|
.vid_ram_sw_cen_i ( vid_ram_sw_cen ), // Video-RAM Software chip enable (active low)
|
| 451 |
|
|
.vid_ram_sw_dout_o ( vid_ram_sw_dout ), // Video-RAM Software data input
|
| 452 |
|
|
|
| 453 |
|
|
// GPU interface (round-robin with refresh-backend)
|
| 454 |
|
|
.vid_ram_gpu_addr_i ( vid_ram_gpu_addr ), // Video-RAM GPU address
|
| 455 |
|
|
.vid_ram_gpu_din_i ( vid_ram_gpu_din ), // Video-RAM GPU data
|
| 456 |
|
|
.vid_ram_gpu_wen_i ( vid_ram_gpu_wen ), // Video-RAM GPU write strobe (active low)
|
| 457 |
|
|
.vid_ram_gpu_cen_i ( vid_ram_gpu_cen ), // Video-RAM GPU chip enable (active low)
|
| 458 |
|
|
.vid_ram_gpu_dout_o ( vid_ram_gpu_dout ), // Video-RAM GPU data input
|
| 459 |
|
|
.vid_ram_gpu_dout_rdy_nxt_o ( vid_ram_gpu_dout_rdy_nxt ), // Video-RAM GPU data output ready during next cycle
|
| 460 |
|
|
|
| 461 |
|
|
// Refresh-backend (round-robin with GPU interface)
|
| 462 |
|
|
.vid_ram_refr_addr_i ( vid_ram_refr_addr ), // Video-RAM Refresh address
|
| 463 |
|
|
.vid_ram_refr_din_i ( 16'h0000 ), // Video-RAM Refresh data
|
| 464 |
|
|
.vid_ram_refr_wen_i ( 1'h1 ), // Video-RAM Refresh write strobe (active low)
|
| 465 |
|
|
.vid_ram_refr_cen_i ( vid_ram_refr_cen ), // Video-RAM Refresh enable (active low)
|
| 466 |
|
|
.vid_ram_refr_dout_o ( vid_ram_refr_dout ), // Video-RAM Refresh data output
|
| 467 |
|
|
.vid_ram_refr_dout_rdy_nxt_o ( vid_ram_refr_dout_rdy_nxt ), // Video-RAM Refresh data output ready during next cycle
|
| 468 |
|
|
|
| 469 |
|
|
// Video Memory interface
|
| 470 |
|
|
.vid_ram_addr_o ( vid_ram_addr_o ), // Video-RAM address
|
| 471 |
|
|
.vid_ram_din_o ( vid_ram_din_o ), // Video-RAM data
|
| 472 |
|
|
.vid_ram_wen_o ( vid_ram_wen_o ), // Video-RAM write strobe (active low)
|
| 473 |
|
|
.vid_ram_cen_o ( vid_ram_cen_o ), // Video-RAM chip enable (active low)
|
| 474 |
|
|
.vid_ram_dout_i ( vid_ram_dout_i ) // Video-RAM data input
|
| 475 |
|
|
|
| 476 |
|
|
//------------------------------------------------------------
|
| 477 |
|
|
);
|
| 478 |
|
|
|
| 479 |
|
|
|
| 480 |
|
|
endmodule // openGFX430
|
| 481 |
|
|
|
| 482 |
|
|
`ifdef OGFX_NO_INCLUDE
|
| 483 |
|
|
`else
|
| 484 |
|
|
`include "openGFX430_undefines.v"
|
| 485 |
|
|
`endif
|
