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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg.v] - Blame information for rev 221

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1 221 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2009 , Olivier Girard
3
//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the authors nor the names of its contributors
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//       may be used to endorse or promote products derived from this software
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//       without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
27
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_dbg.v
31
//
32
// *Module Description:
33
//                       Debug interface
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39
// $Rev$
40
// $LastChangedBy$
41
// $LastChangedDate$
42
//----------------------------------------------------------------------------
43
`ifdef OMSP_NO_INCLUDE
44
`else
45
`include "openMSP430_defines.v"
46
`endif
47
 
48
module  omsp_dbg (
49
 
50
// OUTPUTs
51
    dbg_cpu_reset,                     // Reset CPU from debug interface
52
    dbg_freeze,                        // Freeze peripherals
53
    dbg_halt_cmd,                      // Halt CPU command
54
    dbg_i2c_sda_out,                   // Debug interface: I2C SDA OUT
55
    dbg_mem_addr,                      // Debug address for rd/wr access
56
    dbg_mem_dout,                      // Debug unit data output
57
    dbg_mem_en,                        // Debug unit memory enable
58
    dbg_mem_wr,                        // Debug unit memory write
59
    dbg_reg_wr,                        // Debug unit CPU register write
60
    dbg_uart_txd,                      // Debug interface: UART TXD
61
 
62
// INPUTs
63
    cpu_en_s,                          // Enable CPU code execution (synchronous)
64
    cpu_id,                            // CPU ID
65
    cpu_nr_inst,                       // Current oMSP instance number
66
    cpu_nr_total,                      // Total number of oMSP instances-1
67
    dbg_clk,                           // Debug unit clock
68
    dbg_en_s,                          // Debug interface enable (synchronous)
69
    dbg_halt_st,                       // Halt/Run status from CPU
70
    dbg_i2c_addr,                      // Debug interface: I2C Address
71
    dbg_i2c_broadcast,                 // Debug interface: I2C Broadcast Address (for multicore systems)
72
    dbg_i2c_scl,                       // Debug interface: I2C SCL
73
    dbg_i2c_sda_in,                    // Debug interface: I2C SDA IN
74
    dbg_mem_din,                       // Debug unit Memory data input
75
    dbg_reg_din,                       // Debug unit CPU register data input
76
    dbg_rst,                           // Debug unit reset
77
    dbg_uart_rxd,                      // Debug interface: UART RXD (asynchronous)
78
    decode_noirq,                      // Frontend decode instruction
79
    eu_mab,                            // Execution-Unit Memory address bus
80
    eu_mb_en,                          // Execution-Unit Memory bus enable
81
    eu_mb_wr,                          // Execution-Unit Memory bus write transfer
82
    fe_mdb_in,                         // Frontend Memory data bus input
83
    pc,                                // Program counter
84
    puc_pnd_set                        // PUC pending set for the serial debug interface
85
);
86
 
87
// OUTPUTs
88
//=========
89
output              dbg_cpu_reset;     // Reset CPU from debug interface
90
output              dbg_freeze;        // Freeze peripherals
91
output              dbg_halt_cmd;      // Halt CPU command
92
output              dbg_i2c_sda_out;   // Debug interface: I2C SDA OUT
93
output       [15:0] dbg_mem_addr;      // Debug address for rd/wr access
94
output       [15:0] dbg_mem_dout;      // Debug unit data output
95
output              dbg_mem_en;        // Debug unit memory enable
96
output        [1:0] dbg_mem_wr;        // Debug unit memory write
97
output              dbg_reg_wr;        // Debug unit CPU register write
98
output              dbg_uart_txd;      // Debug interface: UART TXD
99
 
100
// INPUTs
101
//=========
102
input               cpu_en_s;          // Enable CPU code execution (synchronous)
103
input        [31:0] cpu_id;            // CPU ID
104
input         [7:0] cpu_nr_inst;       // Current oMSP instance number
105
input         [7:0] cpu_nr_total;      // Total number of oMSP instances-1
106
input               dbg_clk;           // Debug unit clock
107
input               dbg_en_s;          // Debug interface enable (synchronous)
108
input               dbg_halt_st;       // Halt/Run status from CPU
109
input         [6:0] dbg_i2c_addr;      // Debug interface: I2C Address
110
input         [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
111
input               dbg_i2c_scl;       // Debug interface: I2C SCL
112
input               dbg_i2c_sda_in;    // Debug interface: I2C SDA IN
113
input        [15:0] dbg_mem_din;       // Debug unit Memory data input
114
input        [15:0] dbg_reg_din;       // Debug unit CPU register data input
115
input               dbg_rst;           // Debug unit reset
116
input               dbg_uart_rxd;      // Debug interface: UART RXD (asynchronous)
117
input               decode_noirq;      // Frontend decode instruction
118
input        [15:0] eu_mab;            // Execution-Unit Memory address bus
119
input               eu_mb_en;          // Execution-Unit Memory bus enable
120
input         [1:0] eu_mb_wr;          // Execution-Unit Memory bus write transfer
121
input        [15:0] fe_mdb_in;         // Frontend Memory data bus input
122
input        [15:0] pc;                // Program counter
123
input               puc_pnd_set;       // PUC pending set for the serial debug interface
124
 
125
 
126
//=============================================================================
127
// 1)  WIRE & PARAMETER DECLARATION
128
//=============================================================================
129
 
130
// Diverse wires and registers
131
wire  [5:0] dbg_addr;
132
wire [15:0] dbg_din;
133
wire        dbg_wr;
134
reg         mem_burst;
135
wire        dbg_reg_rd;
136
wire        dbg_mem_rd;
137
reg         dbg_mem_rd_dly;
138
wire        dbg_swbrk;
139
wire        dbg_rd;
140
reg         dbg_rd_rdy;
141
wire        mem_burst_rd;
142
wire        mem_burst_wr;
143
wire        brk0_halt;
144
wire        brk0_pnd;
145
wire [15:0] brk0_dout;
146
wire        brk1_halt;
147
wire        brk1_pnd;
148
wire [15:0] brk1_dout;
149
wire        brk2_halt;
150
wire        brk2_pnd;
151
wire [15:0] brk2_dout;
152
wire        brk3_halt;
153
wire        brk3_pnd;
154
wire [15:0] brk3_dout;
155
 
156
// Number of registers
157
parameter           NR_REG       = 25;
158
 
159
// Register addresses
160
parameter           CPU_ID_LO    = 6'h00;
161
parameter           CPU_ID_HI    = 6'h01;
162
parameter           CPU_CTL      = 6'h02;
163
parameter           CPU_STAT     = 6'h03;
164
parameter           MEM_CTL      = 6'h04;
165
parameter           MEM_ADDR     = 6'h05;
166
parameter           MEM_DATA     = 6'h06;
167
parameter           MEM_CNT      = 6'h07;
168
`ifdef DBG_HWBRK_0
169
parameter           BRK0_CTL     = 6'h08;
170
parameter           BRK0_STAT    = 6'h09;
171
parameter           BRK0_ADDR0   = 6'h0A;
172
parameter           BRK0_ADDR1   = 6'h0B;
173
`endif
174
`ifdef DBG_HWBRK_1
175
parameter           BRK1_CTL     = 6'h0C;
176
parameter           BRK1_STAT    = 6'h0D;
177
parameter           BRK1_ADDR0   = 6'h0E;
178
parameter           BRK1_ADDR1   = 6'h0F;
179
`endif
180
`ifdef DBG_HWBRK_2
181
parameter           BRK2_CTL     = 6'h10;
182
parameter           BRK2_STAT    = 6'h11;
183
parameter           BRK2_ADDR0   = 6'h12;
184
parameter           BRK2_ADDR1   = 6'h13;
185
`endif
186
`ifdef DBG_HWBRK_3
187
parameter           BRK3_CTL     = 6'h14;
188
parameter           BRK3_STAT    = 6'h15;
189
parameter           BRK3_ADDR0   = 6'h16;
190
parameter           BRK3_ADDR1   = 6'h17;
191
`endif
192
parameter           CPU_NR       = 6'h18;
193
 
194
// Register one-hot decoder
195
parameter           BASE_D       = {{NR_REG-1{1'b0}}, 1'b1};
196
parameter           CPU_ID_LO_D  = (BASE_D << CPU_ID_LO);
197
parameter           CPU_ID_HI_D  = (BASE_D << CPU_ID_HI);
198
parameter           CPU_CTL_D    = (BASE_D << CPU_CTL);
199
parameter           CPU_STAT_D   = (BASE_D << CPU_STAT);
200
parameter           MEM_CTL_D    = (BASE_D << MEM_CTL);
201
parameter           MEM_ADDR_D   = (BASE_D << MEM_ADDR);
202
parameter           MEM_DATA_D   = (BASE_D << MEM_DATA);
203
parameter           MEM_CNT_D    = (BASE_D << MEM_CNT);
204
`ifdef DBG_HWBRK_0
205
parameter           BRK0_CTL_D   = (BASE_D << BRK0_CTL);
206
parameter           BRK0_STAT_D  = (BASE_D << BRK0_STAT);
207
parameter           BRK0_ADDR0_D = (BASE_D << BRK0_ADDR0);
208
parameter           BRK0_ADDR1_D = (BASE_D << BRK0_ADDR1);
209
`endif
210
`ifdef DBG_HWBRK_1
211
parameter           BRK1_CTL_D   = (BASE_D << BRK1_CTL);
212
parameter           BRK1_STAT_D  = (BASE_D << BRK1_STAT);
213
parameter           BRK1_ADDR0_D = (BASE_D << BRK1_ADDR0);
214
parameter           BRK1_ADDR1_D = (BASE_D << BRK1_ADDR1);
215
`endif
216
`ifdef DBG_HWBRK_2
217
parameter           BRK2_CTL_D   = (BASE_D << BRK2_CTL);
218
parameter           BRK2_STAT_D  = (BASE_D << BRK2_STAT);
219
parameter           BRK2_ADDR0_D = (BASE_D << BRK2_ADDR0);
220
parameter           BRK2_ADDR1_D = (BASE_D << BRK2_ADDR1);
221
`endif
222
`ifdef DBG_HWBRK_3
223
parameter           BRK3_CTL_D   = (BASE_D << BRK3_CTL);
224
parameter           BRK3_STAT_D  = (BASE_D << BRK3_STAT);
225
parameter           BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
226
parameter           BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
227
`endif
228
parameter           CPU_NR_D     = (BASE_D << CPU_NR);
229
 
230
 
231
//============================================================================
232
// 2)  REGISTER DECODER
233
//============================================================================
234
 
235
// Select Data register during a burst
236
wire  [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
237
 
238
// Register address decode
239
reg  [NR_REG-1:0]  reg_dec;
240
always @(dbg_addr_in)
241
  case (dbg_addr_in)
242
    CPU_ID_LO :  reg_dec  =  CPU_ID_LO_D;
243
    CPU_ID_HI :  reg_dec  =  CPU_ID_HI_D;
244
    CPU_CTL   :  reg_dec  =  CPU_CTL_D;
245
    CPU_STAT  :  reg_dec  =  CPU_STAT_D;
246
    MEM_CTL   :  reg_dec  =  MEM_CTL_D;
247
    MEM_ADDR  :  reg_dec  =  MEM_ADDR_D;
248
    MEM_DATA  :  reg_dec  =  MEM_DATA_D;
249
    MEM_CNT   :  reg_dec  =  MEM_CNT_D;
250
`ifdef DBG_HWBRK_0
251
    BRK0_CTL  :  reg_dec  =  BRK0_CTL_D;
252
    BRK0_STAT :  reg_dec  =  BRK0_STAT_D;
253
    BRK0_ADDR0:  reg_dec  =  BRK0_ADDR0_D;
254
    BRK0_ADDR1:  reg_dec  =  BRK0_ADDR1_D;
255
`endif
256
`ifdef DBG_HWBRK_1
257
    BRK1_CTL  :  reg_dec  =  BRK1_CTL_D;
258
    BRK1_STAT :  reg_dec  =  BRK1_STAT_D;
259
    BRK1_ADDR0:  reg_dec  =  BRK1_ADDR0_D;
260
    BRK1_ADDR1:  reg_dec  =  BRK1_ADDR1_D;
261
`endif
262
`ifdef DBG_HWBRK_2
263
    BRK2_CTL  :  reg_dec  =  BRK2_CTL_D;
264
    BRK2_STAT :  reg_dec  =  BRK2_STAT_D;
265
    BRK2_ADDR0:  reg_dec  =  BRK2_ADDR0_D;
266
    BRK2_ADDR1:  reg_dec  =  BRK2_ADDR1_D;
267
`endif
268
`ifdef DBG_HWBRK_3
269
    BRK3_CTL  :  reg_dec  =  BRK3_CTL_D;
270
    BRK3_STAT :  reg_dec  =  BRK3_STAT_D;
271
    BRK3_ADDR0:  reg_dec  =  BRK3_ADDR0_D;
272
    BRK3_ADDR1:  reg_dec  =  BRK3_ADDR1_D;
273
`endif
274
    CPU_NR    :  reg_dec  =  CPU_NR_D;
275
  // pragma coverage off
276
    default:     reg_dec  =  {NR_REG{1'b0}};
277
  // pragma coverage on
278
  endcase
279
 
280
// Read/Write probes
281
wire               reg_write =  dbg_wr;
282
wire               reg_read  =  1'b1;
283
 
284
// Read/Write vectors
285
wire  [NR_REG-1:0] reg_wr    = reg_dec & {NR_REG{reg_write}};
286
wire  [NR_REG-1:0] reg_rd    = reg_dec & {NR_REG{reg_read}};
287
 
288
 
289
//=============================================================================
290
// 3)  REGISTER: CORE INTERFACE
291
//=============================================================================
292
 
293
// CPU_ID Register
294
//-----------------
295
//              -------------------------------------------------------------------
296
// CPU_ID_LO:  | 15  14  13  12  11  10  9  |  8  7  6  5  4  |  3   |   2  1  0   |
297
//             |----------------------------+-----------------+------+-------------|
298
//             |        PER_SPACE           |   USER_VERSION  | ASIC | CPU_VERSION |
299
//              --------------------------------------------------------------------
300
// CPU_ID_HI:  |   15  14  13  12  11  10   |   9  8  7  6  5  4  3  2  1   |   0  |
301
//             |----------------------------+-------------------------------+------|
302
//             |         PMEM_SIZE          |            DMEM_SIZE          |  MPY |
303
//              -------------------------------------------------------------------
304
 
305
// This register is assigned in the SFR module
306
 
307
 
308
// CPU_NR Register
309
//-----------------
310
//    -------------------------------------------------------------------
311
//   | 15  14  13  12  11  10   9   8  |  7   6   5   4   3   2   1   0  |
312
//   |---------------------------------+---------------------------------|
313
//   |            CPU_TOTAL_NR         |           CPU_INST_NR           |
314
//    -------------------------------------------------------------------
315
 
316
wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
317
 
318
 
319
// CPU_CTL Register
320
//-----------------------------------------------------------------------------
321
//       7         6          5          4           3        2     1    0
322
//   Reserved   CPU_RST  RST_BRK_EN  FRZ_BRK_EN  SW_BRK_EN  ISTEP  RUN  HALT
323
//-----------------------------------------------------------------------------
324
reg   [6:3] cpu_ctl;
325
 
326
wire        cpu_ctl_wr = reg_wr[CPU_CTL];
327
 
328
always @ (posedge dbg_clk or posedge dbg_rst)
329
`ifdef DBG_RST_BRK_EN
330
  if (dbg_rst)         cpu_ctl <=  4'h6;
331
`else
332
  if (dbg_rst)         cpu_ctl <=  4'h2;
333
`endif
334
  else if (cpu_ctl_wr) cpu_ctl <=  dbg_din[6:3];
335
 
336
wire  [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
337
 
338
wire        halt_cpu = cpu_ctl_wr & dbg_din[`HALT]  & ~dbg_halt_st;
339
wire        run_cpu  = cpu_ctl_wr & dbg_din[`RUN]   &  dbg_halt_st;
340
wire        istep    = cpu_ctl_wr & dbg_din[`ISTEP] &  dbg_halt_st;
341
 
342
 
343
// CPU_STAT Register
344
//------------------------------------------------------------------------------------
345
//      7           6          5           4           3         2      1       0
346
// HWBRK3_PND  HWBRK2_PND  HWBRK1_PND  HWBRK0_PND  SWBRK_PND  PUC_PND  Res.  HALT_RUN
347
//------------------------------------------------------------------------------------
348
reg   [3:2] cpu_stat;
349
 
350
wire        cpu_stat_wr  = reg_wr[CPU_STAT];
351
wire  [3:2] cpu_stat_set = {dbg_swbrk, puc_pnd_set};
352
wire  [3:2] cpu_stat_clr = ~dbg_din[3:2];
353
 
354
always @ (posedge dbg_clk or posedge dbg_rst)
355
  if (dbg_rst)          cpu_stat <=  2'b00;
356
  else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
357
  else                  cpu_stat <=  (cpu_stat                 | cpu_stat_set);
358
 
359
wire  [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
360
                             cpu_stat, 1'b0, dbg_halt_st};
361
 
362
 
363
//=============================================================================
364
// 4)  REGISTER: MEMORY INTERFACE
365
//=============================================================================
366
 
367
// MEM_CTL Register
368
//-----------------------------------------------------------------------------
369
//       7     6     5     4          3        2         1       0
370
//            Reserved               B/W    MEM/REG    RD/WR   START
371
//
372
// START  :  -  0 : Do nothing.
373
//           -  1 : Initiate memory transfer.
374
//
375
// RD/WR  :  -  0 : Read access.
376
//           -  1 : Write access.
377
//
378
// MEM/REG:  -  0 : Memory access.
379
//           -  1 : CPU Register access.
380
//
381
// B/W    :  -  0 : 16 bit access.
382
//           -  1 :  8 bit access (not valid for CPU Registers).
383
//
384
//-----------------------------------------------------------------------------
385
reg   [3:1] mem_ctl;
386
 
387
wire        mem_ctl_wr = reg_wr[MEM_CTL];
388
 
389
always @ (posedge dbg_clk or posedge dbg_rst)
390
  if (dbg_rst)         mem_ctl <=  3'h0;
391
  else if (mem_ctl_wr) mem_ctl <=  dbg_din[3:1];
392
 
393
wire  [7:0] mem_ctl_full  = {4'b0000, mem_ctl, 1'b0};
394
 
395
reg         mem_start;
396
always @ (posedge dbg_clk or posedge dbg_rst)
397
  if (dbg_rst)  mem_start <=  1'b0;
398
  else          mem_start <=  mem_ctl_wr & dbg_din[0];
399
 
400
wire        mem_bw    = mem_ctl[3];
401
 
402
// MEM_DATA Register
403
//------------------
404
reg  [15:0] mem_data;
405
reg  [15:0] mem_addr;
406
wire        mem_access;
407
 
408
wire        mem_data_wr = reg_wr[MEM_DATA];
409
 
410
wire [15:0] dbg_mem_din_bw = ~mem_bw      ? dbg_mem_din                :
411
                              mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
412
                                            {8'h00, dbg_mem_din[7:0]};
413
 
414
always @ (posedge dbg_clk or posedge dbg_rst)
415
  if (dbg_rst)             mem_data <=  16'h0000;
416
  else if (mem_data_wr)    mem_data <=  dbg_din;
417
  else if (dbg_reg_rd)     mem_data <=  dbg_reg_din;
418
  else if (dbg_mem_rd_dly) mem_data <=  dbg_mem_din_bw;
419
 
420
 
421
// MEM_ADDR Register
422
//------------------
423
reg  [15:0] mem_cnt;
424
 
425
wire        mem_addr_wr  = reg_wr[MEM_ADDR];
426
wire        dbg_mem_acc  = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
427
wire        dbg_reg_acc  = ( dbg_reg_wr | (dbg_rd_rdy &  mem_ctl[2]));
428
 
429
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000)                       ? 16'h0000 :
430
                           (mem_burst &  dbg_mem_acc & ~mem_bw)      ? 16'h0002 :
431
                           (mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000;
432
 
433
always @ (posedge dbg_clk or posedge dbg_rst)
434
  if (dbg_rst)          mem_addr <=  16'h0000;
435
  else if (mem_addr_wr) mem_addr <=  dbg_din;
436
  else                  mem_addr <=  mem_addr + mem_addr_inc;
437
 
438
// MEM_CNT Register
439
//------------------
440
 
441
wire        mem_cnt_wr  = reg_wr[MEM_CNT];
442
 
443
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000)                       ? 16'h0000 :
444
                          (mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'hffff : 16'h0000;
445
 
446
always @ (posedge dbg_clk or posedge dbg_rst)
447
  if (dbg_rst)         mem_cnt <=  16'h0000;
448
  else if (mem_cnt_wr) mem_cnt <=  dbg_din;
449
  else                 mem_cnt <=  mem_cnt + mem_cnt_dec;
450
 
451
 
452
//=============================================================================
453
// 5)  BREAKPOINTS / WATCHPOINTS
454
//=============================================================================
455
 
456
`ifdef DBG_HWBRK_0
457
// Hardware Breakpoint/Watchpoint Register read select
458
wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
459
                          reg_rd[BRK0_ADDR0],
460
                          reg_rd[BRK0_STAT],
461
                          reg_rd[BRK0_CTL]};
462
 
463
// Hardware Breakpoint/Watchpoint Register write select
464
wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
465
                          reg_wr[BRK0_ADDR0],
466
                          reg_wr[BRK0_STAT],
467
                          reg_wr[BRK0_CTL]};
468
 
469
omsp_dbg_hwbrk dbg_hwbr_0 (
470
 
471
// OUTPUTs
472
    .brk_halt     (brk0_halt),    // Hardware breakpoint command
473
    .brk_pnd      (brk0_pnd),     // Hardware break/watch-point pending
474
    .brk_dout     (brk0_dout),    // Hardware break/watch-point register data input
475
 
476
// INPUTs
477
    .brk_reg_rd   (brk0_reg_rd),  // Hardware break/watch-point register read select
478
    .brk_reg_wr   (brk0_reg_wr),  // Hardware break/watch-point register write select
479
    .dbg_clk      (dbg_clk),      // Debug unit clock
480
    .dbg_din      (dbg_din),      // Debug register data input
481
    .dbg_rst      (dbg_rst),      // Debug unit reset
482
    .decode_noirq (decode_noirq), // Frontend decode instruction
483
    .eu_mab       (eu_mab),       // Execution-Unit Memory address bus
484
    .eu_mb_en     (eu_mb_en),     // Execution-Unit Memory bus enable
485
    .eu_mb_wr     (eu_mb_wr),     // Execution-Unit Memory bus write transfer
486
    .pc           (pc)            // Program counter
487
);
488
 
489
`else
490
assign      brk0_halt       =  1'b0;
491
assign      brk0_pnd        =  1'b0;
492
assign      brk0_dout       = 16'h0000;
493
wire [15:0] UNUSED_eu_mab   =  eu_mab;
494
wire        UNUSED_eu_mb_en =  eu_mb_en;
495
wire  [1:0] UNUSED_eu_mb_wr =  eu_mb_wr;
496
wire [15:0] UNUSED_pc       =  pc;
497
`endif
498
 
499
`ifdef DBG_HWBRK_1
500
// Hardware Breakpoint/Watchpoint Register read select
501
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
502
                          reg_rd[BRK1_ADDR0],
503
                          reg_rd[BRK1_STAT],
504
                          reg_rd[BRK1_CTL]};
505
 
506
// Hardware Breakpoint/Watchpoint Register write select
507
wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
508
                          reg_wr[BRK1_ADDR0],
509
                          reg_wr[BRK1_STAT],
510
                          reg_wr[BRK1_CTL]};
511
 
512
omsp_dbg_hwbrk dbg_hwbr_1 (
513
 
514
// OUTPUTs
515
    .brk_halt     (brk1_halt),    // Hardware breakpoint command
516
    .brk_pnd      (brk1_pnd),     // Hardware break/watch-point pending
517
    .brk_dout     (brk1_dout),    // Hardware break/watch-point register data input
518
 
519
// INPUTs
520
    .brk_reg_rd   (brk1_reg_rd),  // Hardware break/watch-point register read select
521
    .brk_reg_wr   (brk1_reg_wr),  // Hardware break/watch-point register write select
522
    .dbg_clk      (dbg_clk),      // Debug unit clock
523
    .dbg_din      (dbg_din),      // Debug register data input
524
    .dbg_rst      (dbg_rst),      // Debug unit reset
525
    .decode_noirq (decode_noirq), // Frontend decode instruction
526
    .eu_mab       (eu_mab),       // Execution-Unit Memory address bus
527
    .eu_mb_en     (eu_mb_en),     // Execution-Unit Memory bus enable
528
    .eu_mb_wr     (eu_mb_wr),     // Execution-Unit Memory bus write transfer
529
    .pc           (pc)            // Program counter
530
);
531
 
532
`else
533
assign brk1_halt =  1'b0;
534
assign brk1_pnd  =  1'b0;
535
assign brk1_dout = 16'h0000;
536
`endif
537
 
538
 `ifdef DBG_HWBRK_2
539
// Hardware Breakpoint/Watchpoint Register read select
540
wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
541
                          reg_rd[BRK2_ADDR0],
542
                          reg_rd[BRK2_STAT],
543
                          reg_rd[BRK2_CTL]};
544
 
545
// Hardware Breakpoint/Watchpoint Register write select
546
wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
547
                          reg_wr[BRK2_ADDR0],
548
                          reg_wr[BRK2_STAT],
549
                          reg_wr[BRK2_CTL]};
550
 
551
omsp_dbg_hwbrk dbg_hwbr_2 (
552
 
553
// OUTPUTs
554
    .brk_halt     (brk2_halt),    // Hardware breakpoint command
555
    .brk_pnd      (brk2_pnd),     // Hardware break/watch-point pending
556
    .brk_dout     (brk2_dout),    // Hardware break/watch-point register data input
557
 
558
// INPUTs
559
    .brk_reg_rd   (brk2_reg_rd),  // Hardware break/watch-point register read select
560
    .brk_reg_wr   (brk2_reg_wr),  // Hardware break/watch-point register write select
561
    .dbg_clk      (dbg_clk),      // Debug unit clock
562
    .dbg_din      (dbg_din),      // Debug register data input
563
    .dbg_rst      (dbg_rst),      // Debug unit reset
564
    .decode_noirq (decode_noirq), // Frontend decode instruction
565
    .eu_mab       (eu_mab),       // Execution-Unit Memory address bus
566
    .eu_mb_en     (eu_mb_en),     // Execution-Unit Memory bus enable
567
    .eu_mb_wr     (eu_mb_wr),     // Execution-Unit Memory bus write transfer
568
    .pc           (pc)            // Program counter
569
);
570
 
571
`else
572
assign brk2_halt =  1'b0;
573
assign brk2_pnd  =  1'b0;
574
assign brk2_dout = 16'h0000;
575
`endif
576
 
577
`ifdef DBG_HWBRK_3
578
// Hardware Breakpoint/Watchpoint Register read select
579
wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
580
                          reg_rd[BRK3_ADDR0],
581
                          reg_rd[BRK3_STAT],
582
                          reg_rd[BRK3_CTL]};
583
 
584
// Hardware Breakpoint/Watchpoint Register write select
585
wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
586
                          reg_wr[BRK3_ADDR0],
587
                          reg_wr[BRK3_STAT],
588
                          reg_wr[BRK3_CTL]};
589
 
590
omsp_dbg_hwbrk dbg_hwbr_3 (
591
 
592
// OUTPUTs
593
    .brk_halt     (brk3_halt),    // Hardware breakpoint command
594
    .brk_pnd      (brk3_pnd),     // Hardware break/watch-point pending
595
    .brk_dout     (brk3_dout),    // Hardware break/watch-point register data input
596
 
597
// INPUTs
598
    .brk_reg_rd   (brk3_reg_rd),  // Hardware break/watch-point register read select
599
    .brk_reg_wr   (brk3_reg_wr),  // Hardware break/watch-point register write select
600
    .dbg_clk      (dbg_clk),      // Debug unit clock
601
    .dbg_din      (dbg_din),      // Debug register data input
602
    .dbg_rst      (dbg_rst),      // Debug unit reset
603
    .decode_noirq (decode_noirq), // Frontend decode instruction
604
    .eu_mab       (eu_mab),       // Execution-Unit Memory address bus
605
    .eu_mb_en     (eu_mb_en),     // Execution-Unit Memory bus enable
606
    .eu_mb_wr     (eu_mb_wr),     // Execution-Unit Memory bus write transfer
607
    .pc           (pc)            // Program counter
608
);
609
 
610
`else
611
assign brk3_halt =  1'b0;
612
assign brk3_pnd  =  1'b0;
613
assign brk3_dout = 16'h0000;
614
`endif
615
 
616
 
617
//============================================================================
618
// 6) DATA OUTPUT GENERATION
619
//============================================================================
620
 
621
wire [15:0] cpu_id_lo_rd = cpu_id[15:0]           & {16{reg_rd[CPU_ID_LO]}};
622
wire [15:0] cpu_id_hi_rd = cpu_id[31:16]          & {16{reg_rd[CPU_ID_HI]}};
623
wire [15:0] cpu_ctl_rd   = {8'h00, cpu_ctl_full}  & {16{reg_rd[CPU_CTL]}};
624
wire [15:0] cpu_stat_rd  = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
625
wire [15:0] mem_ctl_rd   = {8'h00, mem_ctl_full}  & {16{reg_rd[MEM_CTL]}};
626
wire [15:0] mem_data_rd  = mem_data               & {16{reg_rd[MEM_DATA]}};
627
wire [15:0] mem_addr_rd  = mem_addr               & {16{reg_rd[MEM_ADDR]}};
628
wire [15:0] mem_cnt_rd   = mem_cnt                & {16{reg_rd[MEM_CNT]}};
629
wire [15:0] cpu_nr_rd    = cpu_nr                 & {16{reg_rd[CPU_NR]}};
630
 
631
wire [15:0] dbg_dout = cpu_id_lo_rd |
632
                       cpu_id_hi_rd |
633
                       cpu_ctl_rd   |
634
                       cpu_stat_rd  |
635
                       mem_ctl_rd   |
636
                       mem_data_rd  |
637
                       mem_addr_rd  |
638
                       mem_cnt_rd   |
639
                       brk0_dout    |
640
                       brk1_dout    |
641
                       brk2_dout    |
642
                       brk3_dout    |
643
                       cpu_nr_rd;
644
 
645
// Tell UART/I2C interface that the data is ready to be read
646
always @ (posedge dbg_clk or posedge dbg_rst)
647
  if (dbg_rst)                       dbg_rd_rdy  <=  1'b0;
648
  else if (mem_burst | mem_burst_rd) dbg_rd_rdy  <= (dbg_reg_rd | dbg_mem_rd_dly);
649
  else                               dbg_rd_rdy  <=  dbg_rd;
650
 
651
 
652
//============================================================================
653
// 7) CPU CONTROL
654
//============================================================================
655
 
656
// Reset CPU
657
//--------------------------
658
wire dbg_cpu_reset  = cpu_ctl[`CPU_RST];
659
 
660
 
661
// Break after reset
662
//--------------------------
663
wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_pnd_set;
664
 
665
 
666
// Freeze peripherals
667
//--------------------------
668
wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
669
 
670
 
671
// Software break
672
//--------------------------
673
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
674
 
675
 
676
// Single step
677
//--------------------------
678
reg [1:0] inc_step;
679
always @(posedge dbg_clk or posedge dbg_rst)
680
  if (dbg_rst)    inc_step <= 2'b00;
681
  else if (istep) inc_step <= 2'b11;
682
  else            inc_step <= {inc_step[0], 1'b0};
683
 
684
 
685
// Run / Halt
686
//--------------------------
687
reg   halt_flag;
688
 
689
wire  mem_halt_cpu;
690
wire  mem_run_cpu;
691
 
692
wire  halt_flag_clr = run_cpu   | mem_run_cpu;
693
wire  halt_flag_set = halt_cpu  | halt_rst  | dbg_swbrk | mem_halt_cpu |
694
                      brk0_halt | brk1_halt | brk2_halt | brk3_halt;
695
 
696
always @(posedge dbg_clk or posedge dbg_rst)
697
  if (dbg_rst)            halt_flag <= 1'b0;
698
  else if (halt_flag_clr) halt_flag <= 1'b0;
699
  else if (halt_flag_set) halt_flag <= 1'b1;
700
 
701
wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
702
 
703
 
704
//============================================================================
705
// 8) MEMORY CONTROL
706
//============================================================================
707
 
708
// Control Memory bursts
709
//------------------------------
710
 
711
wire mem_burst_start = (mem_start             &  |mem_cnt);
712
wire mem_burst_end   = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
713
 
714
// Detect when burst is on going
715
always @(posedge dbg_clk or posedge dbg_rst)
716
  if (dbg_rst)              mem_burst <= 1'b0;
717
  else if (mem_burst_start) mem_burst <= 1'b1;
718
  else if (mem_burst_end)   mem_burst <= 1'b0;
719
 
720
// Control signals for UART/I2C interface
721
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
722
assign mem_burst_wr = (mem_burst_start &  mem_ctl[1]);
723
 
724
// Trigger CPU Register or memory access during a burst
725
reg        mem_startb;
726
always @(posedge dbg_clk or posedge dbg_rst)
727
  if (dbg_rst) mem_startb <= 1'b0;
728
  else         mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
729
 
730
// Combine single and burst memory start of sequence
731
wire       mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
732
 
733
 
734
// Memory access state machine
735
//------------------------------
736
reg  [1:0] mem_state;
737
reg  [1:0] mem_state_nxt;
738
 
739
// State machine definition
740
parameter  M_IDLE       = 2'h0;
741
parameter  M_SET_BRK    = 2'h1;
742
parameter  M_ACCESS_BRK = 2'h2;
743
parameter  M_ACCESS     = 2'h3;
744
 
745
// State transition
746
always @(mem_state or mem_seq_start or dbg_halt_st)
747
  case (mem_state)
748
    M_IDLE       : mem_state_nxt = ~mem_seq_start ? M_IDLE       :
749
                                    dbg_halt_st   ? M_ACCESS     : M_SET_BRK;
750
    M_SET_BRK    : mem_state_nxt =  dbg_halt_st   ? M_ACCESS_BRK : M_SET_BRK;
751
    M_ACCESS_BRK : mem_state_nxt =  M_IDLE;
752
    M_ACCESS     : mem_state_nxt =  M_IDLE;
753
  // pragma coverage off
754
    default      : mem_state_nxt =  M_IDLE;
755
  // pragma coverage on
756
  endcase
757
 
758
// State machine
759
always @(posedge dbg_clk or posedge dbg_rst)
760
  if (dbg_rst) mem_state <= M_IDLE;
761
  else         mem_state <= mem_state_nxt;
762
 
763
// Utility signals
764
assign mem_halt_cpu = (mem_state==M_IDLE)       & (mem_state_nxt==M_SET_BRK);
765
assign mem_run_cpu  = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
766
assign mem_access   = (mem_state==M_ACCESS)     | (mem_state==M_ACCESS_BRK);
767
 
768
 
769
// Interface to CPU Registers and Memory bacbkone
770
//------------------------------------------------
771
assign      dbg_mem_addr   =  mem_addr;
772
assign      dbg_mem_dout   = ~mem_bw      ? mem_data               :
773
                              mem_addr[0] ? {mem_data[7:0], 8'h00} :
774
                                            {8'h00, mem_data[7:0]};
775
 
776
assign      dbg_reg_wr     = mem_access &  mem_ctl[1] &  mem_ctl[2];
777
assign      dbg_reg_rd     = mem_access & ~mem_ctl[1] &  mem_ctl[2];
778
 
779
assign      dbg_mem_en     = mem_access & ~mem_ctl[2];
780
assign      dbg_mem_rd     = dbg_mem_en & ~mem_ctl[1];
781
 
782
wire  [1:0] dbg_mem_wr_msk = ~mem_bw      ? 2'b11 :
783
                              mem_addr[0] ? 2'b10 : 2'b01;
784
assign      dbg_mem_wr     = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
785
 
786
 
787
// It takes one additional cycle to read from Memory as from registers
788
always @(posedge dbg_clk or posedge dbg_rst)
789
  if (dbg_rst) dbg_mem_rd_dly <= 1'b0;
790
  else         dbg_mem_rd_dly <= dbg_mem_rd;
791
 
792
 
793
//=============================================================================
794
// 9)  UART COMMUNICATION
795
//=============================================================================
796
`ifdef DBG_UART
797
omsp_dbg_uart dbg_uart_0 (
798
 
799
// OUTPUTs
800
    .dbg_addr         (dbg_addr),         // Debug register address
801
    .dbg_din          (dbg_din),          // Debug register data input
802
    .dbg_rd           (dbg_rd),           // Debug register data read
803
    .dbg_uart_txd     (dbg_uart_txd),     // Debug interface: UART TXD
804
    .dbg_wr           (dbg_wr),           // Debug register data write
805
 
806
// INPUTs
807
    .dbg_clk          (dbg_clk),          // Debug unit clock
808
    .dbg_dout         (dbg_dout),         // Debug register data output
809
    .dbg_rd_rdy       (dbg_rd_rdy),       // Debug register data is ready for read
810
    .dbg_rst          (dbg_rst),          // Debug unit reset
811
    .dbg_uart_rxd     (dbg_uart_rxd),     // Debug interface: UART RXD
812
    .mem_burst        (mem_burst),        // Burst on going
813
    .mem_burst_end    (mem_burst_end),    // End TX/RX burst
814
    .mem_burst_rd     (mem_burst_rd),     // Start TX burst
815
    .mem_burst_wr     (mem_burst_wr),     // Start RX burst
816
    .mem_bw           (mem_bw)            // Burst byte width
817
);
818
 
819
`else
820
    assign dbg_uart_txd        =  1'b1;
821
 
822
    wire   UNUSED_dbg_uart_rxd =  dbg_uart_rxd;
823
 
824
 
825
  `ifdef DBG_I2C
826
  `else
827
    assign dbg_addr            =  6'h00;
828
    assign dbg_din             = 16'h0000;
829
    assign dbg_rd              =  1'b0;
830
    assign dbg_wr              =  1'b0;
831
  `endif
832
`endif
833
 
834
//=============================================================================
835
// 10)  I2C COMMUNICATION
836
//=============================================================================
837
`ifdef DBG_I2C
838
omsp_dbg_i2c dbg_i2c_0 (
839
 
840
// OUTPUTs
841
    .dbg_addr          (dbg_addr),          // Debug register address
842
    .dbg_din           (dbg_din),           // Debug register data input
843
    .dbg_i2c_sda_out   (dbg_i2c_sda_out),   // Debug interface: I2C SDA OUT
844
    .dbg_rd            (dbg_rd),            // Debug register data read
845
    .dbg_wr            (dbg_wr),            // Debug register data write
846
 
847
// INPUTs
848
    .dbg_clk           (dbg_clk),           // Debug unit clock
849
    .dbg_dout          (dbg_dout),          // Debug register data output
850
    .dbg_i2c_addr      (dbg_i2c_addr),      // Debug interface: I2C Address
851
    .dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
852
    .dbg_i2c_scl       (dbg_i2c_scl),       // Debug interface: I2C SCL
853
    .dbg_i2c_sda_in    (dbg_i2c_sda_in),    // Debug interface: I2C SDA IN
854
    .dbg_rst           (dbg_rst),           // Debug unit reset
855
    .mem_burst         (mem_burst),         // Burst on going
856
    .mem_burst_end     (mem_burst_end),     // End TX/RX burst
857
    .mem_burst_rd      (mem_burst_rd),      // Start TX burst
858
    .mem_burst_wr      (mem_burst_wr),      // Start RX burst
859
    .mem_bw            (mem_bw)             // Burst byte width
860
);
861
 
862
`else
863
    assign     dbg_i2c_sda_out          = 1'b1;
864
 
865
    wire [6:0] UNUSED_dbg_i2c_addr      = dbg_i2c_addr;
866
    wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
867
    wire       UNUSED_dbg_i2c_scl       = dbg_i2c_scl;
868
    wire       UNUSED_dbg_i2c_sda_in    = dbg_i2c_sda_in;
869
    wire       UNUSED_dbg_rd_rdy        = dbg_rd_rdy;
870
`endif
871
 
872
endmodule // omsp_dbg
873
 
874
`ifdef OMSP_NO_INCLUDE
875
`else
876
`include "openMSP430_undefines.v"
877
`endif

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