OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_uart.v] - Blame information for rev 221

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 221 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2009 , Olivier Girard
3
//
4
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15
//
16
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_dbg_uart.v
31
//
32
// *Module Description:
33
//                       Debug UART communication interface (8N1, Half-duplex)
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39
// $Rev$
40
// $LastChangedBy$
41
// $LastChangedDate$
42
//----------------------------------------------------------------------------
43
`ifdef OMSP_NO_INCLUDE
44
`else
45
`include "openMSP430_defines.v"
46
`endif
47
 
48
module  omsp_dbg_uart (
49
 
50
// OUTPUTs
51
    dbg_addr,                       // Debug register address
52
    dbg_din,                        // Debug register data input
53
    dbg_rd,                         // Debug register data read
54
    dbg_uart_txd,                   // Debug interface: UART TXD
55
    dbg_wr,                         // Debug register data write
56
 
57
// INPUTs
58
    dbg_clk,                        // Debug unit clock
59
    dbg_dout,                       // Debug register data output
60
    dbg_rd_rdy,                     // Debug register data is ready for read
61
    dbg_rst,                        // Debug unit reset
62
    dbg_uart_rxd,                   // Debug interface: UART RXD
63
    mem_burst,                      // Burst on going
64
    mem_burst_end,                  // End TX/RX burst
65
    mem_burst_rd,                   // Start TX burst
66
    mem_burst_wr,                   // Start RX burst
67
    mem_bw                          // Burst byte width
68
);
69
 
70
// OUTPUTs
71
//=========
72
output        [5:0] dbg_addr;       // Debug register address
73
output       [15:0] dbg_din;        // Debug register data input
74
output              dbg_rd;         // Debug register data read
75
output              dbg_uart_txd;   // Debug interface: UART TXD
76
output              dbg_wr;         // Debug register data write
77
 
78
// INPUTs
79
//=========
80
input               dbg_clk;        // Debug unit clock
81
input        [15:0] dbg_dout;       // Debug register data output
82
input               dbg_rd_rdy;     // Debug register data is ready for read
83
input               dbg_rst;        // Debug unit reset
84
input               dbg_uart_rxd;   // Debug interface: UART RXD
85
input               mem_burst;      // Burst on going
86
input               mem_burst_end;  // End TX/RX burst
87
input               mem_burst_rd;   // Start TX burst
88
input               mem_burst_wr;   // Start RX burst
89
input               mem_bw;         // Burst byte width
90
 
91
 
92
//=============================================================================
93
// 1)  UART RECEIVE LINE SYNCHRONIZTION & FILTERING
94
//=============================================================================
95
 
96
// Synchronize RXD input
97
//--------------------------------
98
`ifdef SYNC_DBG_UART_RXD
99
 
100
    wire uart_rxd_n;
101
 
102
    omsp_sync_cell sync_cell_uart_rxd (
103
        .data_out  (uart_rxd_n),
104
        .data_in   (~dbg_uart_rxd),
105
        .clk       (dbg_clk),
106
        .rst       (dbg_rst)
107
    );
108
    wire uart_rxd = ~uart_rxd_n;
109
`else
110
    wire uart_rxd = dbg_uart_rxd;
111
`endif
112
 
113
// RXD input buffer
114
//--------------------------------
115
reg  [1:0] rxd_buf;
116
always @ (posedge dbg_clk or posedge dbg_rst)
117
  if (dbg_rst) rxd_buf <=  2'h3;
118
  else         rxd_buf <=  {rxd_buf[0], uart_rxd};
119
 
120
// Majority decision
121
//------------------------
122
reg        rxd_maj;
123
 
124
wire       rxd_maj_nxt = (uart_rxd   & rxd_buf[0]) |
125
                         (uart_rxd   & rxd_buf[1]) |
126
                         (rxd_buf[0] & rxd_buf[1]);
127
 
128
always @ (posedge dbg_clk or posedge dbg_rst)
129
  if (dbg_rst) rxd_maj <=  1'b1;
130
  else         rxd_maj <=  rxd_maj_nxt;
131
 
132
wire rxd_s    =  rxd_maj;
133
wire rxd_fe   =  rxd_maj & ~rxd_maj_nxt;
134
wire rxd_re   = ~rxd_maj &  rxd_maj_nxt;
135
wire rxd_edge =  rxd_maj ^  rxd_maj_nxt;
136
 
137
//=============================================================================
138
// 2)  UART STATE MACHINE
139
//=============================================================================
140
 
141
// Receive state
142
//------------------------
143
reg   [2:0] uart_state;
144
reg   [2:0] uart_state_nxt;
145
 
146
wire        sync_done;
147
wire        xfer_done;
148
reg  [19:0] xfer_buf;
149
wire [19:0] xfer_buf_nxt;
150
 
151
// State machine definition
152
parameter  RX_SYNC  = 3'h0;
153
parameter  RX_CMD   = 3'h1;
154
parameter  RX_DATA1 = 3'h2;
155
parameter  RX_DATA2 = 3'h3;
156
parameter  TX_DATA1 = 3'h4;
157
parameter  TX_DATA2 = 3'h5;
158
 
159
// State transition
160
always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
161
  case (uart_state)
162
    RX_SYNC  : uart_state_nxt =  RX_CMD;
163
    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
164
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
165
                                 mem_burst_rd                ?
166
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
167
                                (xfer_buf_nxt[`DBG_UART_WR]  ?
168
                                (xfer_buf_nxt[`DBG_UART_BW]  ? RX_DATA2 : RX_DATA1) :
169
                                (xfer_buf_nxt[`DBG_UART_BW]  ? TX_DATA2 : TX_DATA1));
170
    RX_DATA1 : uart_state_nxt =  RX_DATA2;
171
    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
172
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
173
                                 RX_CMD;
174
    TX_DATA1 : uart_state_nxt =  TX_DATA2;
175
    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
176
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
177
                                 RX_CMD;
178
  // pragma coverage off
179
    default  : uart_state_nxt =  RX_CMD;
180
  // pragma coverage on
181
  endcase
182
 
183
// State machine
184
always @(posedge dbg_clk or posedge dbg_rst)
185
  if (dbg_rst)                          uart_state <= RX_SYNC;
186
  else if (xfer_done    | sync_done |
187
           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
188
 
189
// Utility signals
190
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
191
wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
192
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
193
 
194
 
195
//=============================================================================
196
// 3)  UART SYNCHRONIZATION
197
//=============================================================================
198
// After DBG_RST, the host needs to fist send a synchronization character (0x80)
199
// If this feature doesn't work properly, it is possible to disable it by
200
// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
201
 
202
reg        sync_busy;
203
always @ (posedge dbg_clk or posedge dbg_rst)
204
  if (dbg_rst)                             sync_busy <=  1'b0;
205
  else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <=  1'b1;
206
  else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <=  1'b0;
207
 
208
assign sync_done =  (uart_state==RX_SYNC) & rxd_re & sync_busy;
209
 
210
`ifdef DBG_UART_AUTO_SYNC
211
 
212
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
213
always @ (posedge dbg_clk or posedge dbg_rst)
214
  if (dbg_rst)                                     sync_cnt <=  {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
215
  else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <=  sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
216
 
217
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
218
`else
219
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
220
`endif
221
 
222
 
223
//=============================================================================
224
// 4)  UART RECEIVE / TRANSMIT
225
//=============================================================================
226
 
227
// Transfer counter
228
//------------------------
229
reg                      [3:0] xfer_bit;
230
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
231
 
232
wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
233
wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
234
wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
235
assign     xfer_done    = rx_active ? (xfer_bit==4'ha) : (xfer_bit==4'hb);
236
 
237
always @ (posedge dbg_clk or posedge dbg_rst)
238
  if (dbg_rst)                       xfer_bit <=  4'h0;
239
  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
240
  else if (xfer_done)                xfer_bit <=  4'h0;
241
  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;
242
 
243
always @ (posedge dbg_clk or posedge dbg_rst)
244
  if (dbg_rst)                       xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1'b0}};
245
  else if (rx_active & rxd_edge)     xfer_cnt <=  {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
246
  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
247
  else if (|xfer_cnt)                xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
248
 
249
 
250
// Receive/Transmit buffer
251
//-------------------------
252
assign xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
253
 
254
always @ (posedge dbg_clk or posedge dbg_rst)
255
  if (dbg_rst)           xfer_buf <=  20'h00000;
256
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
257
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
258
 
259
 
260
// Generate TXD output
261
//------------------------
262
reg dbg_uart_txd;
263
 
264
always @ (posedge dbg_clk or posedge dbg_rst)
265
  if (dbg_rst)                       dbg_uart_txd <=  1'b1;
266
  else if (xfer_bit_inc & tx_active) dbg_uart_txd <=  xfer_buf[0];
267
 
268
 
269
//=============================================================================
270
// 5) INTERFACE TO DEBUG REGISTERS
271
//=============================================================================
272
 
273
reg [5:0] dbg_addr;
274
 always @ (posedge dbg_clk or posedge dbg_rst)
275
  if (dbg_rst)        dbg_addr <=  6'h00;
276
  else if (cmd_valid) dbg_addr <=  xfer_buf_nxt[`DBG_UART_ADDR];
277
 
278
reg       dbg_bw;
279
always @ (posedge dbg_clk or posedge dbg_rst)
280
  if (dbg_rst)        dbg_bw   <=  1'b0;
281
  else if (cmd_valid) dbg_bw   <=  xfer_buf_nxt[`DBG_UART_BW];
282
 
283
wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;
284
 
285
wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf_nxt[18:11]} :
286
                                       {xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
287
wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
288
wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
289
                                     (cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;
290
 
291
 
292
 
293
endmodule // omsp_dbg_uart
294
 
295
`ifdef OMSP_NO_INCLUDE
296
`else
297
`include "openMSP430_undefines.v"
298
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.