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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [openmsp430/] [omsp_multiplier.v] - Blame information for rev 221

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1 221 olivier.gi
//----------------------------------------------------------------------------
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// Copyright (C) 2009 , Olivier Girard
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the authors nor the names of its contributors
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//       may be used to endorse or promote products derived from this software
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//       without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: omsp_multiplier.v
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//
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// *Module Description:
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//                       16x16 Hardware multiplier.
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`else
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`include "openMSP430_defines.v"
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`endif
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module  omsp_multiplier (
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// OUTPUTs
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    per_dout,                       // Peripheral data output
52
 
53
// INPUTs
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    mclk,                           // Main system clock
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    per_addr,                       // Peripheral address
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    per_din,                        // Peripheral data input
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    per_en,                         // Peripheral enable (high active)
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    per_we,                         // Peripheral write enable (high active)
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    puc_rst,                        // Main system reset
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    scan_enable                     // Scan enable (active during scan shifting)
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);
62
 
63
// OUTPUTs
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//=========
65
output       [15:0] per_dout;       // Peripheral data output
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67
// INPUTs
68
//=========
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input               mclk;           // Main system clock
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input        [13:0] per_addr;       // Peripheral address
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input        [15:0] per_din;        // Peripheral data input
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input               per_en;         // Peripheral enable (high active)
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input         [1:0] per_we;         // Peripheral write enable (high active)
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input               puc_rst;        // Main system reset
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input               scan_enable;    // Scan enable (active during scan shifting)
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77
 
78
//=============================================================================
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// 1)  PARAMETER/REGISTERS & WIRE DECLARATION
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//=============================================================================
81
 
82
// Register base address (must be aligned to decoder bit width)
83
parameter       [14:0] BASE_ADDR   = 15'h0130;
84
 
85
// Decoder bit width (defines how many bits are considered for address decoding)
86
parameter              DEC_WD      =  4;
87
 
88
// Register addresses offset
89
parameter [DEC_WD-1:0] OP1_MPY     = 'h0,
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                       OP1_MPYS    = 'h2,
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                       OP1_MAC     = 'h4,
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                       OP1_MACS    = 'h6,
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                       OP2         = 'h8,
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                       RESLO       = 'hA,
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                       RESHI       = 'hC,
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                       SUMEXT      = 'hE;
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98
// Register one-hot decoder utilities
99
parameter              DEC_SZ      =  (1 << DEC_WD);
100
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
101
 
102
// Register one-hot decoder
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parameter [DEC_SZ-1:0] OP1_MPY_D   = (BASE_REG << OP1_MPY),
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                       OP1_MPYS_D  = (BASE_REG << OP1_MPYS),
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                       OP1_MAC_D   = (BASE_REG << OP1_MAC),
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                       OP1_MACS_D  = (BASE_REG << OP1_MACS),
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                       OP2_D       = (BASE_REG << OP2),
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                       RESLO_D     = (BASE_REG << RESLO),
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                       RESHI_D     = (BASE_REG << RESHI),
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                       SUMEXT_D    = (BASE_REG << SUMEXT);
111
 
112
 
113
// Wire pre-declarations
114
wire  result_wr;
115
wire  result_clr;
116
wire  early_read;
117
 
118
 
119
//============================================================================
120
// 2)  REGISTER DECODER
121
//============================================================================
122
 
123
// Local register selection
124
wire              reg_sel     =  per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
125
 
126
// Register local address
127
wire [DEC_WD-1:0] reg_addr    =  {per_addr[DEC_WD-2:0], 1'b0};
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129
// Register address decode
130
wire [DEC_SZ-1:0] reg_dec     =  (OP1_MPY_D   &  {DEC_SZ{(reg_addr == OP1_MPY  )}})  |
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                                 (OP1_MPYS_D  &  {DEC_SZ{(reg_addr == OP1_MPYS )}})  |
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                                 (OP1_MAC_D   &  {DEC_SZ{(reg_addr == OP1_MAC  )}})  |
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                                 (OP1_MACS_D  &  {DEC_SZ{(reg_addr == OP1_MACS )}})  |
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                                 (OP2_D       &  {DEC_SZ{(reg_addr == OP2      )}})  |
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                                 (RESLO_D     &  {DEC_SZ{(reg_addr == RESLO    )}})  |
136
                                 (RESHI_D     &  {DEC_SZ{(reg_addr == RESHI    )}})  |
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                                 (SUMEXT_D    &  {DEC_SZ{(reg_addr == SUMEXT   )}});
138
 
139
// Read/Write probes
140
wire              reg_write   =  |per_we & reg_sel;
141
wire              reg_read    = ~|per_we & reg_sel;
142
 
143
// Read/Write vectors
144
wire [DEC_SZ-1:0] reg_wr      = reg_dec & {DEC_SZ{reg_write}};
145
wire [DEC_SZ-1:0] reg_rd      = reg_dec & {DEC_SZ{reg_read}};
146
 
147
// Masked input data for byte access
148
wire       [15:0] per_din_msk =  per_din & {{8{per_we[1]}}, 8'hff};
149
 
150
//============================================================================
151
// 3) REGISTERS
152
//============================================================================
153
 
154
// OP1 Register
155
//-----------------
156
reg  [15:0] op1;
157
 
158
wire        op1_wr = reg_wr[OP1_MPY]  |
159
                     reg_wr[OP1_MPYS] |
160
                     reg_wr[OP1_MAC]  |
161
                     reg_wr[OP1_MACS];
162
 
163
`ifdef CLOCK_GATING
164
wire        mclk_op1;
165
omsp_clock_gate clock_gate_op1 (.gclk(mclk_op1),
166
                                .clk (mclk), .enable(op1_wr), .scan_enable(scan_enable));
167
`else
168
wire        UNUSED_scan_enable = scan_enable;
169
wire        mclk_op1           = mclk;
170
`endif
171
 
172
always @ (posedge mclk_op1 or posedge puc_rst)
173
  if (puc_rst)      op1 <=  16'h0000;
174
`ifdef CLOCK_GATING
175
  else              op1 <=  per_din_msk;
176
`else
177
  else if (op1_wr)  op1 <=  per_din_msk;
178
`endif
179
 
180
wire [15:0] op1_rd  = op1;
181
 
182
 
183
// OP2 Register
184
//-----------------
185
reg  [15:0] op2;
186
 
187
wire        op2_wr = reg_wr[OP2];
188
 
189
`ifdef CLOCK_GATING
190
wire        mclk_op2;
191
omsp_clock_gate clock_gate_op2 (.gclk(mclk_op2),
192
                                .clk (mclk), .enable(op2_wr), .scan_enable(scan_enable));
193
`else
194
wire        mclk_op2 = mclk;
195
`endif
196
 
197
always @ (posedge mclk_op2 or posedge puc_rst)
198
  if (puc_rst)      op2 <=  16'h0000;
199
`ifdef CLOCK_GATING
200
  else              op2 <=  per_din_msk;
201
`else
202
  else if (op2_wr)  op2 <=  per_din_msk;
203
`endif
204
 
205
wire [15:0] op2_rd  = op2;
206
 
207
 
208
// RESLO Register
209
//-----------------
210
reg  [15:0] reslo;
211
 
212
wire [15:0] reslo_nxt;
213
wire        reslo_wr = reg_wr[RESLO];
214
 
215
`ifdef CLOCK_GATING
216
wire        reslo_en = reslo_wr | result_clr | result_wr;
217
wire        mclk_reslo;
218
omsp_clock_gate clock_gate_reslo (.gclk(mclk_reslo),
219
                                  .clk (mclk), .enable(reslo_en), .scan_enable(scan_enable));
220
`else
221
wire        mclk_reslo = mclk;
222
`endif
223
 
224
always @ (posedge mclk_reslo or posedge puc_rst)
225
  if (puc_rst)         reslo <=  16'h0000;
226
  else if (reslo_wr)   reslo <=  per_din_msk;
227
  else if (result_clr) reslo <=  16'h0000;
228
`ifdef CLOCK_GATING
229
  else                 reslo <=  reslo_nxt;
230
`else
231
  else if (result_wr)  reslo <=  reslo_nxt;
232
`endif
233
 
234
wire [15:0] reslo_rd = early_read ? reslo_nxt : reslo;
235
 
236
 
237
// RESHI Register
238
//-----------------
239
reg  [15:0] reshi;
240
 
241
wire [15:0] reshi_nxt;
242
wire        reshi_wr = reg_wr[RESHI];
243
 
244
`ifdef CLOCK_GATING
245
wire        reshi_en = reshi_wr | result_clr | result_wr;
246
wire        mclk_reshi;
247
omsp_clock_gate clock_gate_reshi (.gclk(mclk_reshi),
248
                                  .clk (mclk), .enable(reshi_en), .scan_enable(scan_enable));
249
`else
250
wire        mclk_reshi = mclk;
251
`endif
252
 
253
always @ (posedge mclk_reshi or posedge puc_rst)
254
  if (puc_rst)         reshi <=  16'h0000;
255
  else if (reshi_wr)   reshi <=  per_din_msk;
256
  else if (result_clr) reshi <=  16'h0000;
257
`ifdef CLOCK_GATING
258
  else                 reshi <=  reshi_nxt;
259
`else
260
  else if (result_wr)  reshi <=  reshi_nxt;
261
`endif
262
 
263
wire [15:0] reshi_rd = early_read ? reshi_nxt  : reshi;
264
 
265
 
266
// SUMEXT Register
267
//-----------------
268
reg  [1:0] sumext_s;
269
 
270
wire [1:0] sumext_s_nxt;
271
 
272
always @ (posedge mclk or posedge puc_rst)
273
  if (puc_rst)         sumext_s <=  2'b00;
274
  else if (op2_wr)     sumext_s <=  2'b00;
275
  else if (result_wr)  sumext_s <=  sumext_s_nxt;
276
 
277
wire [15:0] sumext_nxt = {{14{sumext_s_nxt[1]}}, sumext_s_nxt};
278
wire [15:0] sumext     = {{14{sumext_s[1]}},     sumext_s};
279
wire [15:0] sumext_rd  = early_read ? sumext_nxt : sumext;
280
 
281
 
282
//============================================================================
283
// 4) DATA OUTPUT GENERATION
284
//============================================================================
285
 
286
// Data output mux
287
wire [15:0] op1_mux    = op1_rd     & {16{reg_rd[OP1_MPY]  |
288
                                          reg_rd[OP1_MPYS] |
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                                          reg_rd[OP1_MAC]  |
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                                          reg_rd[OP1_MACS]}};
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wire [15:0] op2_mux    = op2_rd     & {16{reg_rd[OP2]}};
292
wire [15:0] reslo_mux  = reslo_rd   & {16{reg_rd[RESLO]}};
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wire [15:0] reshi_mux  = reshi_rd   & {16{reg_rd[RESHI]}};
294
wire [15:0] sumext_mux = sumext_rd  & {16{reg_rd[SUMEXT]}};
295
 
296
wire [15:0] per_dout   = op1_mux    |
297
                         op2_mux    |
298
                         reslo_mux  |
299
                         reshi_mux  |
300
                         sumext_mux;
301
 
302
 
303
//============================================================================
304
// 5) HARDWARE MULTIPLIER FUNCTIONAL LOGIC
305
//============================================================================
306
 
307
// Multiplier configuration
308
//--------------------------
309
 
310
// Detect signed mode
311
reg sign_sel;
312
always @ (posedge mclk_op1 or posedge puc_rst)
313
  if (puc_rst)     sign_sel <=  1'b0;
314
`ifdef CLOCK_GATING
315
  else             sign_sel <=  reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
316
`else
317
  else if (op1_wr) sign_sel <=  reg_wr[OP1_MPYS] | reg_wr[OP1_MACS];
318
`endif
319
 
320
 
321
// Detect accumulate mode
322
reg acc_sel;
323
always @ (posedge mclk_op1 or posedge puc_rst)
324
  if (puc_rst)     acc_sel  <=  1'b0;
325
`ifdef CLOCK_GATING
326
  else             acc_sel  <=  reg_wr[OP1_MAC]  | reg_wr[OP1_MACS];
327
`else
328
  else if (op1_wr) acc_sel  <=  reg_wr[OP1_MAC]  | reg_wr[OP1_MACS];
329
`endif
330
 
331
 
332
// Detect whenever the RESHI and RESLO registers should be cleared
333
assign      result_clr = op2_wr & ~acc_sel;
334
 
335
// Combine RESHI & RESLO
336
wire [31:0] result     = {reshi, reslo};
337
 
338
 
339
// 16x16 Multiplier (result computed in 1 clock cycle)
340
//-----------------------------------------------------
341
`ifdef MPY_16x16
342
 
343
// Detect start of a multiplication
344
reg cycle;
345
always @ (posedge mclk or posedge puc_rst)
346
  if (puc_rst) cycle <=  1'b0;
347
  else         cycle <=  op2_wr;
348
 
349
assign result_wr = cycle;
350
 
351
// Expand the operands to support signed & unsigned operations
352
wire signed [16:0] op1_xp = {sign_sel & op1[15], op1};
353
wire signed [16:0] op2_xp = {sign_sel & op2[15], op2};
354
 
355
 
356
// 17x17 signed multiplication
357
wire signed [33:0] product = op1_xp * op2_xp;
358
 
359
// Accumulate
360
wire [32:0] result_nxt = {1'b0, result} + {1'b0, product[31:0]};
361
 
362
 
363
// Next register values
364
assign reslo_nxt    = result_nxt[15:0];
365
assign reshi_nxt    = result_nxt[31:16];
366
assign sumext_s_nxt =  sign_sel ? {2{result_nxt[31]}} :
367
                                  {1'b0, result_nxt[32]};
368
 
369
 
370
// Since the MAC is completed within 1 clock cycle,
371
// an early read can't happen.
372
assign early_read   = 1'b0;
373
 
374
 
375
// 16x8 Multiplier (result computed in 2 clock cycles)
376
//-----------------------------------------------------
377
`else
378
 
379
// Detect start of a multiplication
380
reg [1:0] cycle;
381
always @ (posedge mclk or posedge puc_rst)
382
  if (puc_rst) cycle <=  2'b00;
383
  else         cycle <=  {cycle[0], op2_wr};
384
 
385
assign result_wr = |cycle;
386
 
387
 
388
// Expand the operands to support signed & unsigned operations
389
wire signed [16:0] op1_xp    = {sign_sel & op1[15], op1};
390
wire signed  [8:0] op2_hi_xp = {sign_sel & op2[15], op2[15:8]};
391
wire signed  [8:0] op2_lo_xp = {              1'b0, op2[7:0]};
392
wire signed  [8:0] op2_xp    = cycle[0] ? op2_hi_xp : op2_lo_xp;
393
 
394
 
395
// 17x9 signed multiplication
396
wire signed [25:0] product    = op1_xp * op2_xp;
397
 
398
wire        [31:0] product_xp = cycle[0] ? {product[23:0], 8'h00} :
399
                                           {{8{sign_sel & product[23]}}, product[23:0]};
400
 
401
// Accumulate
402
wire [32:0] result_nxt  = {1'b0, result} + {1'b0, product_xp[31:0]};
403
 
404
 
405
// Next register values
406
assign reslo_nxt    = result_nxt[15:0];
407
assign reshi_nxt    = result_nxt[31:16];
408
assign sumext_s_nxt =  sign_sel ? {2{result_nxt[31]}} :
409
                                  {1'b0, result_nxt[32] | sumext_s[0]};
410
 
411
// Since the MAC is completed within 2 clock cycle,
412
// an early read can happen during the second cycle.
413
assign early_read   = cycle[1];
414
 
415
`endif
416
 
417
 
418
endmodule // omsp_multiplier
419
 
420
`ifdef OMSP_NO_INCLUDE
421
`else
422
`include "openMSP430_undefines.v"
423
`endif

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