OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [openmsp430/] [periph/] [omsp_timerA_undefines.v] - Blame information for rev 221

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 221 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2009 , Olivier Girard
3
//
4
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15
//
16
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_timerA_undefines.v
31
//
32
// *Module Description:
33
//                      omsp_timerA Verilog `undef file
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39
// $Rev: 23 $
40
// $LastChangedBy: olivier.girard $
41
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
42
//----------------------------------------------------------------------------
43
 
44
//----------------------------------------------------------------------------
45
// SYSTEM CONFIGURATION
46
//----------------------------------------------------------------------------
47
 
48
 
49
 
50
//==========================================================================//
51
//==========================================================================//
52
//==========================================================================//
53
//==========================================================================//
54
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
55
//==========================================================================//
56
//==========================================================================//
57
//==========================================================================//
58
//==========================================================================//
59
 
60
// Timer A: TACTL Control Register
61
`ifdef TASSELx
62
`undef TASSELx
63
`endif
64
`ifdef TAIDx
65
`undef TAIDx
66
`endif
67
`ifdef TAMCx
68
`undef TAMCx
69
`endif
70
`ifdef TACLR
71
`undef TACLR
72
`endif
73
`ifdef TAIE
74
`undef TAIE
75
`endif
76
`ifdef TAIFG
77
`undef TAIFG
78
`endif
79
 
80
// Timer A: TACCTLx Capture/Compare Control Register
81
`ifdef TACMx
82
`undef TACMx
83
`endif
84
`ifdef TACCISx
85
`undef TACCISx
86
`endif
87
`ifdef TASCS
88
`undef TASCS
89
`endif
90
`ifdef TASCCI
91
`undef TASCCI
92
`endif
93
`ifdef TACAP
94
`undef TACAP
95
`endif
96
`ifdef TAOUTMODx
97
`undef TAOUTMODx
98
`endif
99
`ifdef TACCIE
100
`undef TACCIE
101
`endif
102
`ifdef TACCI
103
`undef TACCI
104
`endif
105
`ifdef TAOUT
106
`undef TAOUT
107
`endif
108
`ifdef TACOV
109
`undef TACOV
110
`endif
111
`ifdef TACCIFG
112
`undef TACCIFG
113
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.