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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: sync_debouncer.v
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//
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// *Module Description:
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// Super basic 10ms debouncer.
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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module sync_debouncer_10ms (
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// OUTPUTs
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signal_debounced, // Synchronized and 10ms debounced signal
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// INPUTs
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clk_50mhz, // 50MHz clock
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rst, // reset
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signal_async // Asynchonous signal
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);
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// OUTPUTs
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//=========
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output signal_debounced; // Synchronized and 10ms debounced signal
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// INPUTs
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//=========
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input clk_50mhz; // 50MHz clock
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input rst; // reset
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input signal_async; // Asynchonous signal
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// Synchronize signal
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reg [1:0] sync_stage;
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always @(posedge clk_50mhz or posedge rst)
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if (rst) sync_stage <= 2'b00;
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else sync_stage <= {sync_stage[0], signal_async};
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wire signal_sync = sync_stage[1];
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// Debouncer (10.48ms = 0x7ffff x 50MHz clock cycles)
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reg [18:0] debounce_counter;
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always @(posedge clk_50mhz or posedge rst)
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if (rst) debounce_counter <= 19'h00000;
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else if(signal_debounced==signal_sync) debounce_counter <= 19'h00000;
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else debounce_counter <= debounce_counter+1;
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wire debounce_counter_done = (debounce_counter==19'h7ffff);
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// Output signal
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reg signal_debounced;
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always @(posedge clk_50mhz or posedge rst)
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if (rst) signal_debounced <= 1'b0;
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else if(debounce_counter_done) signal_debounced <= ~signal_debounced;
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endmodule
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