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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [sim/] [rtl_sim/] [src/] [leds.v] - Blame information for rev 221

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Line No. Rev Author Line
1 221 olivier.gi
/*===========================================================================*/
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/*                                 DIGITAL I/O                               */
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/*---------------------------------------------------------------------------*/
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/* Test the Digital I/O interface.                                           */
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/*===========================================================================*/
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`define NO_TIMEOUT
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge FPGA_CLK1_50);
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      stimulus_done = 0;
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      //repeat(100) @(posedge FPGA_CLK1_50);
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      #(10000000.0);
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      stimulus_done = 1;
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      force omsp_inst_pc =16'hffff;
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      stimulus_done = 1;
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   end

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