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olivier.gi |
//=============================================================================
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// Copyright (C) 2016 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//-----------------------------------------------------------------------------
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//
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// File Name: submit.f
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//
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// Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//-----------------------------------------------------------------------------
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// $Rev: 136 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
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//=============================================================================
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//=============================================================================
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// Testbench related
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//=============================================================================
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+incdir+../../../bench/verilog/
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../../../bench/verilog/tb_openMSP430_fpga.v
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../../../bench/verilog/msp_debug.v
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//=============================================================================
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// Altera library
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//=============================================================================
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+libext+.v
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../../../bench/verilog/altsyncram.v
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../../../bench/verilog/cyclonev_io.v
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//=============================================================================
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// FPGA Specific modules
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//=============================================================================
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+incdir+../../../rtl/verilog/
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../../../rtl/verilog/openMSP430_fpga.v
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../../../rtl/verilog/omsp_de0_nano_soc_led_key_sw.v
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../../../rtl/verilog/sync_debouncer_10ms.v
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../../../rtl/verilog/mega/ram_16x75k.v
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../../../rtl/verilog/mega/ram_16x512.v
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../../../rtl/verilog/mega/ram_16x16k.v
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../../../rtl/verilog/mega/ram_16x8k.v
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../../../rtl/verilog/mega/io_buf.v
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../../../rtl/verilog/mega/in_buf.v
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//=============================================================================
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// openMSP430
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//=============================================================================
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+incdir+../../../rtl/verilog/openmsp430/
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+incdir+../../../rtl/verilog/openmsp430/periph/
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../../../rtl/verilog/openmsp430/openMSP430.v
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../../../rtl/verilog/openmsp430/omsp_frontend.v
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../../../rtl/verilog/openmsp430/omsp_execution_unit.v
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../../../rtl/verilog/openmsp430/omsp_register_file.v
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../../../rtl/verilog/openmsp430/omsp_alu.v
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../../../rtl/verilog/openmsp430/omsp_sfr.v
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../../../rtl/verilog/openmsp430/omsp_mem_backbone.v
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../../../rtl/verilog/openmsp430/omsp_clock_module.v
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../../../rtl/verilog/openmsp430/omsp_dbg.v
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../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
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../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
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../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v
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../../../rtl/verilog/openmsp430/omsp_watchdog.v
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../../../rtl/verilog/openmsp430/omsp_multiplier.v
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../../../rtl/verilog/openmsp430/omsp_sync_reset.v
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../../../rtl/verilog/openmsp430/omsp_sync_cell.v
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../../../rtl/verilog/openmsp430/omsp_scan_mux.v
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../../../rtl/verilog/openmsp430/omsp_and_gate.v
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../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v
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../../../rtl/verilog/openmsp430/omsp_clock_gate.v
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../../../rtl/verilog/openmsp430/omsp_clock_mux.v
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../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
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//=============================================================================
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// openGFX430
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//=============================================================================
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+incdir+../../../rtl/verilog/opengfx430/
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../../../rtl/verilog/opengfx430/openGFX430.v
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../../../rtl/verilog/opengfx430/ogfx_reg.v
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../../../rtl/verilog/opengfx430/ogfx_reg_fifo.v
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../../../rtl/verilog/opengfx430/ogfx_reg_vram_if.v
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../../../rtl/verilog/opengfx430/ogfx_reg_vram_addr.v
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../../../rtl/verilog/opengfx430/ogfx_if_lt24.v
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../../../rtl/verilog/opengfx430/ogfx_backend.v
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../../../rtl/verilog/opengfx430/ogfx_backend_frame_fifo.v
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../../../rtl/verilog/opengfx430/ogfx_backend_lut_fifo.v
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../../../rtl/verilog/opengfx430/ogfx_gpu.v
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../../../rtl/verilog/opengfx430/ogfx_gpu_reg.v
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../../../rtl/verilog/opengfx430/ogfx_gpu_dma.v
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../../../rtl/verilog/opengfx430/ogfx_gpu_dma_addr.v
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../../../rtl/verilog/opengfx430/ogfx_ram_arbiter.v
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