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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [synthesis/] [altera/] [scripts/] [design.sdc] - Blame information for rev 221

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1 221 olivier.gi
#**************************************************************
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# This .sdc file is created by Terasic Tool.
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# Users are recommended to modify this file to match users logic.
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#**************************************************************
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
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create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
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# for enhancing USB BlasterII to be reliable, 25MHz
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#create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
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#set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
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#set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
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#set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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#**************************************************************
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# Set Load
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#**************************************************************

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