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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ram.v
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//
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// *Module Description:
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// Scalable RAM model
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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module ram_16x1k_dp (
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clka,
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ena,
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wea,
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addra,
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dina,
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douta,
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clkb,
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enb,
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web,
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addrb,
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dinb,
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doutb
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);
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input clka;
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input ena;
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input [1 : 0] wea;
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input [9 : 0] addra;
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input [15 : 0] dina;
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output [15 : 0] douta;
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input clkb;
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input enb;
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input [1 : 0] web;
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input [9 : 0] addrb;
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input [15 : 0] dinb;
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output [15 : 0] doutb;
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//============
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// RAM
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//============
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ram_dp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_dp_inst (
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// OUTPUTs
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.ram_douta ( douta), // RAM data output (Port A)
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.ram_doutb ( douta), // RAM data output (Port B)
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// INPUTs
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.ram_addra ( addra), // RAM address (Port A)
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.ram_cena (~ena), // RAM chip enable (low active) (Port A)
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.ram_clka ( clka), // RAM clock (Port A)
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.ram_dina ( dina), // RAM data input (Port A)
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.ram_wena (~wea), // RAM write enable (low active) (Port A)
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.ram_addrb ( addrb), // RAM address (Port B)
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.ram_cenb (~enb), // RAM chip enable (low active) (Port B)
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.ram_clkb ( clkb), // RAM clock (Port B)
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.ram_dinb ( dinb), // RAM data input (Port B)
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.ram_wenb (~web) // RAM write enable (low active) (Port B)
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);
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endmodule // ram_16x1k_dp
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