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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [bench/] [verilog/] [ram_16x1k_sp.v] - Blame information for rev 213

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: ram.v
// 
// *Module Description:
//                      Scalable RAM model
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
 
module ram_16x1k_sp (
  clka,
  ena,
  wea,
  addra,
  dina,
  douta
);
 
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
 
//============
// RAM
//============
 
ram_sp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_sp_inst (
 
// OUTPUTs
    .ram_dout     ( douta),      // RAM data output
 
// INPUTs
    .ram_addr     ( addra),      // RAM address
    .ram_cen      (~ena),        // RAM chip enable (low active)
    .ram_clk      ( clka),       // RAM clock
    .ram_din      ( dina),       // RAM data input
    .ram_wen      (~wea)         // RAM write enable (low active)
);
 
 
endmodule // ram_16x1k_sp
 

Line No.	Rev	Author	Line
1	167	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: ram.v`
26			`//`
27			`// *Module Description:`
28			`// Scalable RAM model`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34			`// $Rev: 103 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $`
37			`//----------------------------------------------------------------------------`
38
39			`module ram_16x1k_sp (`
40			`clka,`
41			`ena,`
42			`wea,`
43			`addra,`
44			`dina,`
45			`douta`
46			`);`
47
48			`input clka;`
49			`input ena;`
50			`input [1 : 0] wea;`
51			`input [9 : 0] addra;`
52			`input [15 : 0] dina;`
53			`output [15 : 0] douta;`
54
55			`//============`
56			`// RAM`
57			`//============`
58
59			`ram_sp #(.ADDR_MSB(9), .MEM_SIZE(2048)) ram_sp_inst (`
60
61			`// OUTPUTs`
62			`.ram_dout ( douta), // RAM data output`
63
64			`// INPUTs`
65			`.ram_addr ( addra), // RAM address`
66			`.ram_cen (~ena), // RAM chip enable (low active)`
67			`.ram_clk ( clka), // RAM clock`
68			`.ram_din ( dina), // RAM data input`
69			`.ram_wen (~wea) // RAM write enable (low active)`
70			`);`
71
72
73			`endmodule // ram_16x1k_sp`
74

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [bench/] [verilog/] [ram_16x1k_sp.v] - Blame information for rev 213