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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [bench/] [verilog/] [registers_omsp0.v] - Blame information for rev 167

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Line No. Rev Author Line
1 167 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: registers.v
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//
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// *Module Description:
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//                      Direct connections to internal registers & memory.
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//
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 143 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-05-09 22:20:03 +0200 (Wed, 09 May 2012) $
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//----------------------------------------------------------------------------
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// CPU registers
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//======================
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wire       [15:0] omsp0_r0    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r0;
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wire       [15:0] omsp0_r1    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r1;
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wire       [15:0] omsp0_r2    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r2;
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wire       [15:0] omsp0_r3    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r3;
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wire       [15:0] omsp0_r4    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r4;
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wire       [15:0] omsp0_r5    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r5;
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wire       [15:0] omsp0_r6    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r6;
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wire       [15:0] omsp0_r7    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r7;
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wire       [15:0] omsp0_r8    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r8;
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wire       [15:0] omsp0_r9    = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r9;
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wire       [15:0] omsp0_r10   = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r10;
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wire       [15:0] omsp0_r11   = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r11;
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wire       [15:0] omsp0_r12   = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r12;
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wire       [15:0] omsp0_r13   = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r13;
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wire       [15:0] omsp0_r14   = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r14;
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wire       [15:0] omsp0_r15   = dut.omsp_system_0_inst.openMSP430_0.execution_unit_0.register_file_0.r15;
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// Data Memory cells
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//======================
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wire       [15:0] omsp0_mem200 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[0];
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wire       [15:0] omsp0_mem202 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[1];
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wire       [15:0] omsp0_mem204 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[2];
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wire       [15:0] omsp0_mem206 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[3];
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wire       [15:0] omsp0_mem208 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[4];
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wire       [15:0] omsp0_mem20A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[5];
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wire       [15:0] omsp0_mem20C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[6];
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wire       [15:0] omsp0_mem20E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[7];
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wire       [15:0] omsp0_mem210 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[8];
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wire       [15:0] omsp0_mem212 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[9];
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wire       [15:0] omsp0_mem214 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[10];
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wire       [15:0] omsp0_mem216 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[11];
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wire       [15:0] omsp0_mem218 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[12];
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wire       [15:0] omsp0_mem21A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[13];
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wire       [15:0] omsp0_mem21C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[14];
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wire       [15:0] omsp0_mem21E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[15];
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wire       [15:0] omsp0_mem220 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[16];
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wire       [15:0] omsp0_mem222 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[17];
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wire       [15:0] omsp0_mem224 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[18];
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wire       [15:0] omsp0_mem226 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[19];
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wire       [15:0] omsp0_mem228 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[20];
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wire       [15:0] omsp0_mem22A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[21];
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wire       [15:0] omsp0_mem22C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[22];
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wire       [15:0] omsp0_mem22E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[23];
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wire       [15:0] omsp0_mem230 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[24];
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wire       [15:0] omsp0_mem232 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[25];
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wire       [15:0] omsp0_mem234 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[26];
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wire       [15:0] omsp0_mem236 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[27];
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wire       [15:0] omsp0_mem238 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[28];
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wire       [15:0] omsp0_mem23A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[29];
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wire       [15:0] omsp0_mem23C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[30];
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wire       [15:0] omsp0_mem23E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[31];
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wire       [15:0] omsp0_mem240 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[32];
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wire       [15:0] omsp0_mem242 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[33];
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wire       [15:0] omsp0_mem244 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[34];
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wire       [15:0] omsp0_mem246 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[35];
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wire       [15:0] omsp0_mem248 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[36];
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wire       [15:0] omsp0_mem24A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[37];
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wire       [15:0] omsp0_mem24C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[38];
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wire       [15:0] omsp0_mem24E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[39];
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wire       [15:0] omsp0_mem250 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[40];
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wire       [15:0] omsp0_mem252 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[41];
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wire       [15:0] omsp0_mem254 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[42];
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wire       [15:0] omsp0_mem256 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[43];
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wire       [15:0] omsp0_mem258 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[44];
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wire       [15:0] omsp0_mem25A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[45];
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wire       [15:0] omsp0_mem25C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[46];
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wire       [15:0] omsp0_mem25E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[47];
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wire       [15:0] omsp0_mem260 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[48];
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wire       [15:0] omsp0_mem262 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[49];
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wire       [15:0] omsp0_mem264 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[50];
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wire       [15:0] omsp0_mem266 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[51];
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wire       [15:0] omsp0_mem268 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[52];
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wire       [15:0] omsp0_mem26A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[53];
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wire       [15:0] omsp0_mem26C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[54];
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wire       [15:0] omsp0_mem26E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[55];
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wire       [15:0] omsp0_mem270 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[56];
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wire       [15:0] omsp0_mem272 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[57];
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wire       [15:0] omsp0_mem274 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[58];
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wire       [15:0] omsp0_mem276 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[59];
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wire       [15:0] omsp0_mem278 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[60];
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wire       [15:0] omsp0_mem27A = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[61];
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wire       [15:0] omsp0_mem27C = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[62];
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wire       [15:0] omsp0_mem27E = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[63];
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wire       [15:0] omsp0_mem280 = dut.ram_16x1k_sp_dmem_omsp0.ram_sp_inst.mem[64];
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// Program Memory cells
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//======================
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reg   [15:0] pmem [0:8191];
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// Interrupt vectors
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wire  [15:0] irq_vect_15 = pmem[(1<<(`PMEM_MSB+1))-1];  // RESET Vector
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wire  [15:0] irq_vect_14 = pmem[(1<<(`PMEM_MSB+1))-2];  // NMI
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wire  [15:0] irq_vect_13 = pmem[(1<<(`PMEM_MSB+1))-3];  // IRQ 13
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wire  [15:0] irq_vect_12 = pmem[(1<<(`PMEM_MSB+1))-4];  // IRQ 12
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wire  [15:0] irq_vect_11 = pmem[(1<<(`PMEM_MSB+1))-5];  // IRQ 11
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wire  [15:0] irq_vect_10 = pmem[(1<<(`PMEM_MSB+1))-6];  // IRQ 10
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wire  [15:0] irq_vect_09 = pmem[(1<<(`PMEM_MSB+1))-7];  // IRQ  9
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wire  [15:0] irq_vect_08 = pmem[(1<<(`PMEM_MSB+1))-8];  // IRQ  8
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wire  [15:0] irq_vect_07 = pmem[(1<<(`PMEM_MSB+1))-9];  // IRQ  7
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wire  [15:0] irq_vect_06 = pmem[(1<<(`PMEM_MSB+1))-10]; // IRQ  6
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wire  [15:0] irq_vect_05 = pmem[(1<<(`PMEM_MSB+1))-11]; // IRQ  5
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wire  [15:0] irq_vect_04 = pmem[(1<<(`PMEM_MSB+1))-12]; // IRQ  4
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wire  [15:0] irq_vect_03 = pmem[(1<<(`PMEM_MSB+1))-13]; // IRQ  3
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wire  [15:0] irq_vect_02 = pmem[(1<<(`PMEM_MSB+1))-14]; // IRQ  2
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wire  [15:0] irq_vect_01 = pmem[(1<<(`PMEM_MSB+1))-15]; // IRQ  1
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wire  [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ  0
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// Interrupt detection
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wire              omsp0_nmi_detect  = dut.omsp_system_0_inst.openMSP430_0.frontend_0.nmi_pnd;
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wire              omsp0_irq_detect  = dut.omsp_system_0_inst.openMSP430_0.frontend_0.irq_detect;
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// Debug interface
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wire              omsp0_dbg_en      = dut.omsp_system_0_inst.openMSP430_0.dbg_en;
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wire              omsp0_dbg_clk     = dut.omsp_system_0_inst.openMSP430_0.clock_module_0.dbg_clk;
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wire              omsp0_dbg_rst     = dut.omsp_system_0_inst.openMSP430_0.clock_module_0.dbg_rst;
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// CPU internals
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//======================
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wire omsp0_mclk     = dut.omsp_system_0_inst.openMSP430_0.mclk;
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wire omsp0_puc_rst  = dut.omsp_system_0_inst.openMSP430_0.puc_rst;

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