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olivier.gi |
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# _____
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# / \
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# /____ \____
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# / \===\ \==/
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# /___\===\___\/ AVNET Design Resource Center
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# \======/ www.em.avnet.com/s6microboard
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# \====/
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# ----------------------------------------------------------------------------
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#
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# Created With Avnet UCF Generator V0.3.0
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# Date: Friday, November 12, 2010
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# Time: 4:11:53 PM
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#
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# Updates
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# 4 Jan 2011 -- added DIPs; changed IOSTANDARD for LEDs and LPDDR
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# 11 Jan 2011 -- Changed IOSTANDARD for DIPs to LVCMOS33.
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# Replaced '#' on the end of net names with '_n'
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# 14 Jan 2011 -- Added I2C for CDCE913 clock chip
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# Added formatting and section breaks
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# 27 Jan 2011 -- Updated URL for PMODs
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# 04 Aug 2011 -- Renaming USER_RESET_N to USER_RESET since it is not low-enabled;
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# Added extra comment on Ethernet PHY RXD pull-ups
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# Removed extraneous quote mark in I2C port syntax
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#
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# This design is the property of Avnet. Publication of this
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# design is not authorized without written consent from Avnet.
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#
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# Please direct any questions to:
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# Avnet Technical Forums
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# http://community.em.avnet.com/t5/Spartan-6-LX9-MicroBoard/bd-p/Spartan-6LX9MicroBoard
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#
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# Avnet Centralized Technical Support
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# Centralized-Support@avnet.com
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# 1-800-422-9023
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#
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# Disclaimer:
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# Avnet, Inc. makes no warranty for the use of this code or design.
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# This code is provided "As Is". Avnet, Inc assumes no responsibility for
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# any errors, which may appear in this code, nor does it make a commitment
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# to update the information contained herein. Avnet, Inc specifically
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# disclaims any implied warranties of fitness for a particular purpose.
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# Copyright(c) 2011 Avnet, Inc.
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# All rights reserved.
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#
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# ----------------------------------------------------------------------------
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############################################################################
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# VCC AUX VOLTAGE
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############################################################################
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CONFIG VCCAUX=3.3;
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############################################################################
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# User Reset Push Button
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# Ignore the timing for this signal
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# Internal pull-down required since external resistor is not populated
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############################################################################
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NET USER_RESET LOC = V4 | IOSTANDARD = LVCMOS33 | PULLDOWN; # "USER_RESET"
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NET USER_RESET TIG;
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############################################################################
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# Micron N25Q128 SPI Flash
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# This is a Multi-I/O Flash. Several pins have dual purposes
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# depending on the mode.
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############################################################################
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NET SPI_SCK LOC = R15 | IOSTANDARD = LVCMOS33; # "CCLK"
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NET SPI_CS_n LOC = V3 | IOSTANDARD = LVCMOS33; # "SPI_CS#"
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NET SPI_MOSI_MISO0 LOC = T13 | IOSTANDARD = LVCMOS33; # "MOSI_MISO0"
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NET SPI_MISO_MISO1 LOC = R13 | IOSTANDARD = LVCMOS33; # "D0_DIN_MISO_MISO1"
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NET SPI_Wn_MISO2 LOC = T14 | IOSTANDARD = LVCMOS33; # "D1_MISO2"
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NET SPI_HOLDn_MISO3 LOC = V14 | IOSTANDARD = LVCMOS33; # "D2_MISO3"
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############################################################################
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# Texas Instruments CDCE913 Triple-Output PLL Clock Chip
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# Y1: 40 MHz, USER_CLOCK can be used as external configuration clock
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# Y2: 66.667 MHz
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# Y3: 100 MHz
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############################################################################
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NET USER_CLOCK LOC = V10 | IOSTANDARD = LVCMOS33; # "USER_CLOCK"
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NET CLOCK_Y2 LOC = K15 | IOSTANDARD = LVCMOS33; # "CLOCK_Y2"
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NET CLOCK_Y3 LOC = C10 | IOSTANDARD = LVCMOS33; # "CLOCK_Y3"
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NET USER_CLOCK TNM_NET = USER_CLOCK;
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TIMESPEC TS_USER_CLOCK = PERIOD USER_CLOCK 40000 kHz;
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NET CLOCK_Y2 TNM_NET = CLOCK_Y2;
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TIMESPEC TS_CLOCK_Y2 = PERIOD CLOCK_Y2 66666.7 kHz;
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NET CLOCK_Y3 TNM_NET = CLOCK_Y3;
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TIMESPEC TS_CLOCK_Y3 = PERIOD CLOCK_Y3 100000 kHz;
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############################################################################
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# The following oscillator is not populated in production but the footprint
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# is compatible with the Maxim DS1088LU
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############################################################################
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NET BACKUP_CLK LOC = R8 | IOSTANDARD = LVCMOS33; # "MAIN_CLK"
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############################################################################
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# User DIP Switch x4
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# Internal pull-down required since external resistor is not populated
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############################################################################
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NET GPIO_DIP1 LOC = B3 | IOSTANDARD = LVCMOS33 | PULLDOWN; # "GPIO_DIP1"
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NET GPIO_DIP2 LOC = A3 | IOSTANDARD = LVCMOS33 | PULLDOWN; # "GPIO_DIP2"
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NET GPIO_DIP3 LOC = B4 | IOSTANDARD = LVCMOS33 | PULLDOWN; # "GPIO_DIP3"
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NET GPIO_DIP4 LOC = A4 | IOSTANDARD = LVCMOS33 | PULLDOWN; # "GPIO_DIP4"
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############################################################################
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# User LEDs
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############################################################################
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NET GPIO_LED1 LOC = P4 | IOSTANDARD = LVCMOS18; # "GPIO_LED1"
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NET GPIO_LED2 LOC = L6 | IOSTANDARD = LVCMOS18; # "GPIO_LED2"
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NET GPIO_LED3 LOC = F5 | IOSTANDARD = LVCMOS18; # "GPIO_LED3"
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NET GPIO_LED4 LOC = C2 | IOSTANDARD = LVCMOS18; # "GPIO_LED4"
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############################################################################
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# Silicon Labs CP2102 USB-to-UART Bridge Chip
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############################################################################
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NET USB_RS232_RXD LOC = R7 | IOSTANDARD = LVCMOS33; # "USB_RS232_RXD"
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NET USB_RS232_TXD LOC = T7 | IOSTANDARD = LVCMOS33; # "USB_RS232_TXD"
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############################################################################
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# Texas Instruments CDCE913 programming port
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# Internal pull-ups required since external resistors are not populated
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############################################################################
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NET SCL LOC=P12 | IOSTANDARD = LVCMOS33 | PULLUP; # "SCL"
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NET SDA LOC=U13 | IOSTANDARD = LVCMOS33 | PULLUP; # "SDA"
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############################################################################
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# Micron MT46H32M16LFBF-5 LPDDR
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############################################################################
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CONFIG MCB_PERFORMANCE= STANDARD;
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# Addresses
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NET LPDDR_A0 LOC = J7 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A0"
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NET LPDDR_A1 LOC = J6 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A1"
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NET LPDDR_A2 LOC = H5 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A2"
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NET LPDDR_A3 LOC = L7 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A3"
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NET LPDDR_A4 LOC = F3 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A4"
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NET LPDDR_A5 LOC = H4 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A5"
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NET LPDDR_A6 LOC = H3 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A6"
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NET LPDDR_A7 LOC = H6 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A7"
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NET LPDDR_A8 LOC = D2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A8"
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NET LPDDR_A9 LOC = D1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A9"
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NET LPDDR_A10 LOC = F4 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A10"
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NET LPDDR_A11 LOC = D3 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A11"
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NET LPDDR_A12 LOC = G6 | IOSTANDARD = MOBILE_DDR; # "LPDDR_A12"
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NET LPDDR_BA0 LOC = F2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_BA0"
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NET LPDDR_BA1 LOC = F1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_BA1"
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# Data
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NET LPDDR_DQ0 LOC = L2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ0"
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NET LPDDR_DQ1 LOC = L1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ1"
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NET LPDDR_DQ2 LOC = K2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ2"
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NET LPDDR_DQ3 LOC = K1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ3"
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NET LPDDR_DQ4 LOC = H2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ4"
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NET LPDDR_DQ5 LOC = H1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ5"
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NET LPDDR_DQ6 LOC = J3 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ6"
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NET LPDDR_DQ7 LOC = J1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ7"
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NET LPDDR_DQ8 LOC = M3 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ8"
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NET LPDDR_DQ9 LOC = M1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ9"
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NET LPDDR_DQ10 LOC = N2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ10"
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NET LPDDR_DQ11 LOC = N1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ11"
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NET LPDDR_DQ12 LOC = T2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ12"
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NET LPDDR_DQ13 LOC = T1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ13"
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NET LPDDR_DQ14 LOC = U2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ14"
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NET LPDDR_DQ15 LOC = U1 | IOSTANDARD = MOBILE_DDR; # "LPDDR_DQ15"
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NET LPDDR_LDM LOC = K3 | IOSTANDARD = MOBILE_DDR; # "LPDDR_LDM"
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NET LPDDR_UDM LOC = K4 | IOSTANDARD = MOBILE_DDR; # "LPDDR_UDM"
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NET LPDDR_LDQS LOC = L4 | IOSTANDARD = MOBILE_DDR; # "LPDDR_LDQS"
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NET LPDDR_UDQS LOC = P2 | IOSTANDARD = MOBILE_DDR; # "LPDDR_UDQS"
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# Clock
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NET LPDDR_CK_N LOC = G1 | IOSTANDARD = DIFF_MOBILE_DDR; # "LPDDR_CK_N"
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NET LPDDR_CK_P LOC = G3 | IOSTANDARD = DIFF_MOBILE_DDR; # "LPDDR_CK_P"
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NET LPDDR_CKE LOC = H7 | IOSTANDARD = MOBILE_DDR; # "LPDDR_CKE"
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# Control
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NET LPDDR_CAS_n LOC = K5 | IOSTANDARD = MOBILE_DDR; # "LPDDR_CAS#"
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NET LPDDR_RAS_n LOC = L5 | IOSTANDARD = MOBILE_DDR; # "LPDDR_RAS#"
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NET LPDDR_WE_n LOC = E3 | IOSTANDARD = MOBILE_DDR; # "LPDDR_WE#"
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NET LPDDR_RZQ LOC = N4 | IOSTANDARD = MOBILE_DDR; # "LPDDR_RZQ"
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############################################################################
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# All the IO resources in an IO tile which contains DQSP/UDQSP are used
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# irrespective of a single-ended or differential DQS design. Any signal that
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# is connected to the free pin of the same IO tile in a single-ended design
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# will be unrouted. Hence, the IOB cannot used as general pupose IO.
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############################################################################
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CONFIG PROHIBIT = P1,L3;
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############################################################################
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# National Semiconductor DP83848J 10/100 Ethernet PHY
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# Pull-ups on RXD are necessary to set the PHY AD to 11110b.
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# Must keep the PHY from defaulting to PHY AD = 00000b
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# because this is Isolate Mode
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############################################################################
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NET ETH_COL LOC = M18 | IOSTANDARD = LVCMOS33 | PULLDOWN; # "ETH_COL"
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NET ETH_CRS LOC = N17 | IOSTANDARD = LVCMOS33 | PULLDOWN; # "ETH_CRS"
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NET ETH_MDC LOC = M16 | IOSTANDARD = LVCMOS33; # "ETH_MDC"
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NET ETH_MDIO LOC = L18 | IOSTANDARD = LVCMOS33; # "ETH_MDIO"
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NET ETH_RESET_n LOC = T18 | IOSTANDARD = LVCMOS33 | TIG; # "ETH_RESET#"
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NET ETH_RX_CLK LOC = L15 | IOSTANDARD = LVCMOS33; # "ETH_RX_CLK"
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NET ETH_RX_D0 LOC = T17 | IOSTANDARD = LVCMOS33 | PULLUP; # "ETH_RX_D0"
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NET ETH_RX_D1 LOC = N16 | IOSTANDARD = LVCMOS33 | PULLUP; # "ETH_RX_D1"
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NET ETH_RX_D2 LOC = N15 | IOSTANDARD = LVCMOS33 | PULLUP; # "ETH_RX_D2"
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NET ETH_RX_D3 LOC = P18 | IOSTANDARD = LVCMOS33 | PULLUP; # "ETH_RX_D3"
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NET ETH_RX_DV LOC = P17 | IOSTANDARD = LVCMOS33; # "ETH_RX_DV"
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NET ETH_RX_ER LOC = N18 | IOSTANDARD = LVCMOS33; # "ETH_RX_ER"
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NET ETH_TX_CLK LOC = H17 | IOSTANDARD = LVCMOS33; # "ETH_TX_CLK"
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NET ETH_TX_D0 LOC = K18 | IOSTANDARD = LVCMOS33; # "ETH_TX_D0"
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NET ETH_TX_D1 LOC = K17 | IOSTANDARD = LVCMOS33; # "ETH_TX_D1"
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NET ETH_TX_D2 LOC = J18 | IOSTANDARD = LVCMOS33; # "ETH_TX_D2"
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NET ETH_TX_D3 LOC = J16 | IOSTANDARD = LVCMOS33; # "ETH_TX_D3"
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NET ETH_TX_EN LOC = L17 | IOSTANDARD = LVCMOS33; # "ETH_TX_EN"
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############################################################################
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# Peripheral Modules and GPIO
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# Peripheral Modules (PMODs) were invented by Digilent Inc. as small,
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# inexpensive add-on boards for FPGA development boards. With costs
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# starting as low as $10, PMODs allow you to add a number of capabilities
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# to your board, including A/D, D/A, Wireless Radio, SD Card, 2x16
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# Character LCD and a variety of LEDs, switches, and headers. See the
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# complete library of Digilent PMODs at
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# https://www.digilentinc.com/PMODs
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############################################################################
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# Connector J5
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NET PMOD1_P1 LOC = F15 | IOSTANDARD = LVCMOS33; # "PMOD1_P1"
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NET PMOD1_P2 LOC = F16 | IOSTANDARD = LVCMOS33; # "PMOD1_P2"
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NET PMOD1_P3 LOC = C17 | IOSTANDARD = LVCMOS33; # "PMOD1_P3"
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NET PMOD1_P4 LOC = C18 | IOSTANDARD = LVCMOS33; # "PMOD1_P4"
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NET PMOD1_P7 LOC = F14 | IOSTANDARD = LVCMOS33; # "PMOD1_P7"
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NET PMOD1_P8 LOC = G14 | IOSTANDARD = LVCMOS33; # "PMOD1_P8"
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NET PMOD1_P9 LOC = D17 | IOSTANDARD = LVCMOS33; # "PMOD1_P9"
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NET PMOD1_P10 LOC = D18 | IOSTANDARD = LVCMOS33; # "PMOD1_P10"
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# Connector J4
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NET PMOD2_P1 LOC = H12 | IOSTANDARD = LVCMOS33; # "PMOD2_P1"
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NET PMOD2_P2 LOC = G13 | IOSTANDARD = LVCMOS33; # "PMOD2_P2"
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NET PMOD2_P3 LOC = E16 | IOSTANDARD = LVCMOS33; # "PMOD2_P3"
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NET PMOD2_P4 LOC = E18 | IOSTANDARD = LVCMOS33; # "PMOD2_P4"
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NET PMOD2_P7 LOC = K12 | IOSTANDARD = LVCMOS33; # "PMOD2_P7"
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NET PMOD2_P8 LOC = K13 | IOSTANDARD = LVCMOS33; # "PMOD2_P8"
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NET PMOD2_P9 LOC = F17 | IOSTANDARD = LVCMOS33; # "PMOD2_P9"
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NET PMOD2_P10 LOC = F18 | IOSTANDARD = LVCMOS33; # "PMOD2_P10"
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