OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [coregen.cgc] - Blame information for rev 157

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Line No. Rev Author Line
1 157 olivier.gi
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   xilinx.com
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   CoreGen
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   coregen
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   1.0
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         ram_16x512
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11
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            ram_16x512
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            Native
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            AXI4_Full
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            Memory_Slave
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            false
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            4
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            Single_Port_RAM
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            false
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            No_ECC
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            false
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            false
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            false
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            Single_Bit_Error_Injection
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            true
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            8
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            Minimum_Area
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            8kx2
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            false
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            16
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            512
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            16
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            WRITE_FIRST
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            Use_ENA_Pin
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            16
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            16
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            WRITE_FIRST
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            Always_Enabled
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            false
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            false
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            false
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            false
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            false
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            false
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            false
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            false
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            0
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            false
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            no_coe_file_loaded
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            false
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            0
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            false
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            false
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            CE
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            0
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            false
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            false
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            CE
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            0
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            SYNC
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            false
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            100
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            50
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            100
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            50
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            100
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            100
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            ALL
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            false
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            false
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            spartan6
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            spartan6
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            /home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/
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            0
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            1
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            0
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            0
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            4
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            0
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            8
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            1
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            1
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            0
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            no_coe_file_loaded
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            0
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            0
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            SYNC
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            0
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            CE
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            0
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            0
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            1
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            0
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            1
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            2
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            WRITE_FIRST
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            16
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            16
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            512
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            512
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            9
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            0
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            CE
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            0
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            0
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            0
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            0
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            1
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            2
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            WRITE_FIRST
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            16
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            16
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            512
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            512
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            9
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            ALL
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            0
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            0
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            0
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            0
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                  coregen
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                  ./
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                  ./tmp/
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                  ./tmp/_cg/
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                  xc6slx9
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                  spartan6
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                  csg324
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                  -2
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                  BusFormatAngleBracketNotRipped
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                  Verilog
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                  true
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                  Foundation_ISE
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                  false
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                  false
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                  false
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                  Ngc
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                  false
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                  Behavioral
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                  Verilog
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                  false
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                  2012-06-25+21:54
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                  customization_generator
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                     ./summary.log
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                     unknown
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                     Wed Aug 08 21:11:01 GMT 2012
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                     0xF3CDD37E
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                     generationID_4013899584
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                  view_readme_generator
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                  apply_current_project_options_generator
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                  model_parameter_resolution_generator
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                     ./summary.log
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                     unknown
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                     Wed Aug 08 21:13:17 GMT 2012
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                     0xF3CDD37E
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                     generationID_1879581046
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                  ip_xco_generator
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                     ./ram_16x512.xco
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                     xco
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                     Wed Aug 08 21:13:17 GMT 2012
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                     0xA867FBD4
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                     generationID_1879581046
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                  associated_files_generator
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                     ./ram_16x512/blk_mem_gen_v7_2_readme.txt
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                     ignore
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                     txt
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                     Sat Jul 21 06:10:41 GMT 2012
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                     0x5661B352
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                     generationID_1879581046
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                     ./ram_16x512/doc/blk_mem_gen_v7_2_vinfo.html
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                     ignore
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                     unknown
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                     Sat Jul 21 06:10:41 GMT 2012
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                     0x4D7A616C
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                     generationID_1879581046
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                     ./ram_16x512/doc/pg058-blk-mem-gen.pdf
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                     ignore
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                     pdf
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                     Sat Jul 21 06:10:41 GMT 2012
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                     0xAE5E57E0
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                     generationID_1879581046
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                  ejava_generator
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                     ./ram_16x512/example_design/ram_16x512_exdes.ucf
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                     ignore
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                     ucf
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0xC44C6B6D
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                     generationID_1879581046
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                     ./ram_16x512/example_design/ram_16x512_exdes.vhd
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                     ignore
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                     vhdl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0xE3C0EAFF
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                     generationID_1879581046
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                     ./ram_16x512/example_design/ram_16x512_exdes.xdc
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                     ignore
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                     xdc
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x7684D6D4
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                     generationID_1879581046
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                     ./ram_16x512/example_design/ram_16x512_prod.vhd
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                     ignore
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                     vhdl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x18595B83
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                     generationID_1879581046
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                     ./ram_16x512/implement/implement.bat
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x9B9E25DC
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                     generationID_1879581046
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                     ./ram_16x512/implement/implement.sh
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x8B9D9D57
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                     generationID_1879581046
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                     ./ram_16x512/implement/planAhead_ise.bat
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x7ACBFFA1
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                     generationID_1879581046
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                     ./ram_16x512/implement/planAhead_ise.sh
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x6DFBA35D
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                     generationID_1879581046
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                     ./ram_16x512/implement/planAhead_ise.tcl
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                     ignore
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                     tcl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x7B52EE1C
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                     generationID_1879581046
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                     ./ram_16x512/implement/xst.prj
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0xD9EAD804
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                     generationID_1879581046
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                     ./ram_16x512/implement/xst.scr
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0xD5D7BAC3
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                     generationID_1879581046
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                     ./ram_16x512/simulation/addr_gen.vhd
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                     ignore
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                     vhdl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x886696A8
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                     generationID_1879581046
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                     ./ram_16x512/simulation/bmg_stim_gen.vhd
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                     ignore
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                     vhdl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x2FFFA2F0
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                     generationID_1879581046
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                     ./ram_16x512/simulation/bmg_tb_pkg.vhd
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                     ignore
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                     vhdl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0xD4F2B061
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                     generationID_1879581046
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                     ./ram_16x512/simulation/checker.vhd
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                     ignore
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                     vhdl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x2A8E7144
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                     generationID_1879581046
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                     ./ram_16x512/simulation/data_gen.vhd
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                     ignore
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                     vhdl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0xE0759FCA
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/simcmds.tcl
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                     ignore
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                     tcl
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x6B4676B9
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/simulate_isim.sh
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0xBE113553
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/simulate_mti.bat
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x86EA5D67
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/simulate_mti.do
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x87B7E125
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/simulate_mti.sh
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x86EA5D67
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/simulate_ncsim.sh
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x81AF21C2
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/simulate_vcs.sh
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x05EDBB79
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/ucli_commands.key
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                     ignore
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                     unknown
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                     Wed Aug 08 21:13:18 GMT 2012
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                     0x9434BB5A
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                     generationID_1879581046
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                     ./ram_16x512/simulation/functional/vcs_session.tcl
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                     ignore
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                     tcl
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                     Wed Aug 08 21:13:18 GMT 2012
429 
                     0x230F2A4A
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                     generationID_1879581046
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432
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                     ./ram_16x512/simulation/functional/wave_mti.do
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                     ignore
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                     unknown
436 
                     Wed Aug 08 21:13:18 GMT 2012
437 
                     0xF048DDD2
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                     generationID_1879581046
439
440
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                     ./ram_16x512/simulation/functional/wave_ncsim.sv
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                     ignore
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                     unknown
444 
                     Wed Aug 08 21:13:18 GMT 2012
445 
                     0xCB80E76F
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                     generationID_1879581046
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448
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                     ./ram_16x512/simulation/ram_16x512_synth.vhd
450 
                     ignore
451 
                     vhdl
452 
                     Wed Aug 08 21:13:18 GMT 2012
453 
                     0x41649DFD
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                     generationID_1879581046
455
456
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                     ./ram_16x512/simulation/ram_16x512_tb.vhd
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                     ignore
459 
                     vhdl
460 
                     Wed Aug 08 21:13:18 GMT 2012
461 
                     0x6CDB1B5F
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                     generationID_1879581046
463
464
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                     ./ram_16x512/simulation/random.vhd
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                     ignore
467 
                     vhdl
468 
                     Wed Aug 08 21:13:18 GMT 2012
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                     0xE1CDC376
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                     generationID_1879581046
471
472
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                     ./ram_16x512/simulation/timing/simcmds.tcl
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                     ignore
475 
                     tcl
476 
                     Wed Aug 08 21:13:18 GMT 2012
477 
                     0x6B4676B9
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                     generationID_1879581046
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480
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                     ./ram_16x512/simulation/timing/simulate_isim.sh
482 
                     ignore
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                     unknown
484 
                     Wed Aug 08 21:13:18 GMT 2012
485 
                     0x10CFAA49
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                     generationID_1879581046
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488
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                     ./ram_16x512/simulation/timing/simulate_mti.bat
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                     ignore
491 
                     unknown
492 
                     Wed Aug 08 21:13:18 GMT 2012
493 
                     0x86EA5D67
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                     generationID_1879581046
495
496
497 
                     ./ram_16x512/simulation/timing/simulate_mti.do
498 
                     ignore
499 
                     unknown
500 
                     Wed Aug 08 21:13:18 GMT 2012
501 
                     0x46A6CEE9
502 
                     generationID_1879581046
503
504
505 
                     ./ram_16x512/simulation/timing/simulate_mti.sh
506 
                     ignore
507 
                     unknown
508 
                     Wed Aug 08 21:13:18 GMT 2012
509 
                     0x86EA5D67
510 
                     generationID_1879581046
511
512
513 
                     ./ram_16x512/simulation/timing/simulate_ncsim.sh
514 
                     ignore
515 
                     unknown
516 
                     Wed Aug 08 21:13:18 GMT 2012
517 
                     0x9CF0B215
518 
                     generationID_1879581046
519
520
521 
                     ./ram_16x512/simulation/timing/simulate_vcs.sh
522 
                     ignore
523 
                     unknown
524 
                     Wed Aug 08 21:13:18 GMT 2012
525 
                     0x5EF692D9
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                     generationID_1879581046
527
528
529 
                     ./ram_16x512/simulation/timing/ucli_commands.key
530 
                     ignore
531 
                     unknown
532 
                     Wed Aug 08 21:13:18 GMT 2012
533 
                     0x9434BB5A
534 
                     generationID_1879581046
535
536
537 
                     ./ram_16x512/simulation/timing/vcs_session.tcl
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                     ignore
539 
                     tcl
540 
                     Wed Aug 08 21:13:18 GMT 2012
541 
                     0xEA78A00C
542 
                     generationID_1879581046
543
544
545 
                     ./ram_16x512/simulation/timing/wave_mti.do
546 
                     ignore
547 
                     unknown
548 
                     Wed Aug 08 21:13:18 GMT 2012
549 
                     0x3CE56E2D
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                     generationID_1879581046
551
552
553 
                     ./ram_16x512/simulation/timing/wave_ncsim.sv
554 
                     ignore
555 
                     unknown
556 
                     Wed Aug 08 21:13:18 GMT 2012
557 
                     0x7B82EFD3
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                     generationID_1879581046
559
560
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                  ngc_netlist_generator
563
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                     ./ram_16x512.ngc
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                     ngc
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                     Wed Aug 08 21:14:06 GMT 2012
567 
                     0x4370BDB6
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                     generationID_1879581046
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570
571
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                  obfuscate_netlist_generator
573
574
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                  padded_implementation_netlist_generator
576
577
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                  instantiation_template_generator
579
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                     ./ram_16x512.veo
581 
                     veo
582 
                     Wed Aug 08 21:14:07 GMT 2012
583 
                     0xE2746DB0
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                     generationID_1879581046
585
586
587
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                  synthesis_instantiation_wrapper_generator
589
590 
                     ./ram_16x512_synth.v
591 
                     verilog
592 
                     verilogSynthesis
593 
                     Wed Aug 08 21:14:07 GMT 2012
594 
                     0xC582CA75
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                     generationID_1879581046
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597
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                  structural_simulation_model_generator
600
601 
                     ./ram_16x512.v
602 
                     verilog
603 
                     Wed Aug 08 21:14:07 GMT 2012
604 
                     0xA7EFF1D0
605 
                     generationID_1879581046
606
607
608
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                  all_documents_generator
610
611
612 
                  asy_generator
613
614 
                     ./ram_16x512.asy
615 
                     asy
616 
                     Wed Aug 08 21:14:10 GMT 2012
617 
                     0xD92CF898
618 
                     generationID_1879581046
619
620
621 
                     ./summary.log
622 
                     unknown
623 
                     Wed Aug 08 21:14:10 GMT 2012
624 
                     0xF3CDD37E
625 
                     generationID_1879581046
626
627
628
629 
                  xmdf_generator
630
631 
                     ./ram_16x512_xmdf.tcl
632 
                     tclXmdf
633 
                     tcl
634 
                     Wed Aug 08 21:14:10 GMT 2012
635 
                     0x96576944
636 
                     generationID_1879581046
637
638
639
640 
                  synthesis_ise_generator
641
642 
                     ./ram_16x512.gise
643 
                     ignore
644 
                     gise
645 
                     Wed Aug 08 21:14:15 GMT 2012
646 
                     0x879AE5C3
647 
                     generationID_1879581046
648
649
650 
                     ./ram_16x512.xise
651 
                     ignore
652 
                     xise
653 
                     Wed Aug 08 21:14:15 GMT 2012
654 
                     0x21D19D21
655 
                     generationID_1879581046
656
657
658
659 
                  ise_generator
660
661 
                     ./ram_16x512.gise
662 
                     ignore
663 
                     gise
664 
                     Wed Aug 08 21:14:19 GMT 2012
665 
                     0x96A35546
666 
                     generationID_1879581046
667
668
669 
                     ./ram_16x512.xise
670 
                     ignore
671 
                     xise
672 
                     Wed Aug 08 21:14:19 GMT 2012
673 
                     0x4125196C
674 
                     generationID_1879581046
675
676
677
678 
                  deliver_readme_generator
679
680
681 
                  flist_generator
682
683 
                     ./ram_16x512_flist.txt
684 
                     ignore
685 
                     txtFlist
686 
                     txt
687 
                     Wed Aug 08 21:14:19 GMT 2012
688 
                     0xDC157605
689 
                     generationID_1879581046
690
691
692
693
694
695
696 
         ram_16x2k
697
698
699 
            ram_16x2k
700 
            Native
701 
            AXI4_Full
702 
            Memory_Slave
703 
            false
704 
            4
705 
            Single_Port_RAM
706 
            false
707 
            No_ECC
708 
            false
709 
            false
710 
            false
711 
            Single_Bit_Error_Injection
712 
            true
713 
            8
714 
            Minimum_Area
715 
            8kx2
716 
            false
717 
            16
718 
            2048
719 
            16
720 
            WRITE_FIRST
721 
            Use_ENA_Pin
722 
            16
723 
            16
724 
            WRITE_FIRST
725 
            Always_Enabled
726 
            false
727 
            false
728 
            false
729 
            false
730 
            false
731 
            false
732 
            false
733 
            false
734 
            0
735 
            false
736 
            no_coe_file_loaded
737 
            false
738 
            0
739 
            false
740 
            false
741 
            CE
742 
            0
743 
            false
744 
            false
745 
            CE
746 
            0
747 
            SYNC
748 
            false
749 
            100
750 
            50
751 
            100
752 
            50
753 
            100
754 
            100
755 
            ALL
756 
            false
757 
            false
758 
            spartan6
759 
            spartan6
760 
            /home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/
761 
            0
762 
            1
763 
            0
764 
            0
765 
            4
766 
            0
767 
            8
768 
            1
769 
            1
770 
            0
771 
            no_coe_file_loaded
772 
            0
773 
            0
774 
            SYNC
775 
            0
776 
            CE
777 
            0
778 
            0
779 
            1
780 
            0
781 
            1
782 
            2
783 
            WRITE_FIRST
784 
            16
785 
            16
786 
            2048
787 
            2048
788 
            11
789 
            0
790 
            CE
791 
            0
792 
            0
793 
            0
794 
            0
795 
            1
796 
            2
797 
            WRITE_FIRST
798 
            16
799 
            16
800 
            2048
801 
            2048
802 
            11
803 
            0
804 
            0
805 
            0
806 
            0
807 
            0
808 
            0
809 
            0
810 
            0
811 
            0
812 
            0
813 
            ALL
814 
            0
815 
            0
816 
            0
817 
            0
818
819
820
821
822 
                  coregen
823 
                  ./
824 
                  ./tmp/
825 
                  ./tmp/_cg/
826
827
828 
                  xc6slx9
829 
                  spartan6
830 
                  csg324
831 
                  -2
832
833
834 
                  BusFormatAngleBracketNotRipped
835 
                  Verilog
836 
                  true
837 
                  Foundation_ISE
838 
                  false
839 
                  false
840 
                  false
841 
                  Ngc
842 
                  false
843
844
845 
                  Behavioral
846 
                  Verilog
847 
                  false
848
849
850 
                  2012-06-25+21:54
851
852
853
854
855 
                  apply_current_project_options_generator
856
857
858 
                  customization_generator
859
860 
                     ./summary.log
861 
                     unknown
862 
                     Wed Aug 08 21:16:23 GMT 2012
863 
                     0xE0AD8EEC
864 
                     generationID_3673615094
865
866
867
868 
                  model_parameter_resolution_generator
869
870 
                     ./summary.log
871 
                     unknown
872 
                     Wed Aug 08 21:16:28 GMT 2012
873 
                     0xE0AD8EEC
874 
                     generationID_3673615094
875
876
877
878 
                  ip_xco_generator
879
880 
                     ./ram_16x2k.xco
881 
                     xco
882 
                     Wed Aug 08 21:16:28 GMT 2012
883 
                     0x85968655
884 
                     generationID_3673615094
885
886
887
888 
                  associated_files_generator
889
890 
                     ./ram_16x2k/blk_mem_gen_v7_2_readme.txt
891 
                     ignore
892 
                     txt
893 
                     Sat Jul 21 06:10:41 GMT 2012
894 
                     0x5661B352
895 
                     generationID_3673615094
896
897
898 
                     ./ram_16x2k/doc/blk_mem_gen_v7_2_vinfo.html
899 
                     ignore
900 
                     unknown
901 
                     Sat Jul 21 06:10:41 GMT 2012
902 
                     0x4D7A616C
903 
                     generationID_3673615094
904
905
906 
                     ./ram_16x2k/doc/pg058-blk-mem-gen.pdf
907 
                     ignore
908 
                     pdf
909 
                     Sat Jul 21 06:10:41 GMT 2012
910 
                     0xAE5E57E0
911 
                     generationID_3673615094
912
913
914
915 
                  ejava_generator
916
917 
                     ./ram_16x2k/example_design/ram_16x2k_exdes.ucf
918 
                     ignore
919 
                     ucf
920 
                     Wed Aug 08 21:16:29 GMT 2012
921 
                     0xC44C6B6D
922 
                     generationID_3673615094
923
924
925 
                     ./ram_16x2k/example_design/ram_16x2k_exdes.vhd
926 
                     ignore
927 
                     vhdl
928 
                     Wed Aug 08 21:16:29 GMT 2012
929 
                     0xB53EBA56
930 
                     generationID_3673615094
931
932
933 
                     ./ram_16x2k/example_design/ram_16x2k_exdes.xdc
934 
                     ignore
935 
                     xdc
936 
                     Wed Aug 08 21:16:29 GMT 2012
937 
                     0x7684D6D4
938 
                     generationID_3673615094
939
940
941 
                     ./ram_16x2k/example_design/ram_16x2k_prod.vhd
942 
                     ignore
943 
                     vhdl
944 
                     Wed Aug 08 21:16:29 GMT 2012
945 
                     0x6615EF5D
946 
                     generationID_3673615094
947
948
949 
                     ./ram_16x2k/implement/implement.bat
950 
                     ignore
951 
                     unknown
952 
                     Wed Aug 08 21:16:29 GMT 2012
953 
                     0x05DDF4B6
954 
                     generationID_3673615094
955
956
957 
                     ./ram_16x2k/implement/implement.sh
958 
                     ignore
959 
                     unknown
960 
                     Wed Aug 08 21:16:29 GMT 2012
961 
                     0xF097CEEE
962 
                     generationID_3673615094
963
964
965 
                     ./ram_16x2k/implement/planAhead_ise.bat
966 
                     ignore
967 
                     unknown
968 
                     Wed Aug 08 21:16:29 GMT 2012
969 
                     0x63E08FB1
970 
                     generationID_3673615094
971
972
973 
                     ./ram_16x2k/implement/planAhead_ise.sh
974 
                     ignore
975 
                     unknown
976 
                     Wed Aug 08 21:16:29 GMT 2012
977 
                     0x5FF10142
978 
                     generationID_3673615094
979
980
981 
                     ./ram_16x2k/implement/planAhead_ise.tcl
982 
                     ignore
983 
                     tcl
984 
                     Wed Aug 08 21:16:29 GMT 2012
985 
                     0x9BC544F6
986 
                     generationID_3673615094
987
988
989 
                     ./ram_16x2k/implement/xst.prj
990 
                     ignore
991 
                     unknown
992 
                     Wed Aug 08 21:16:29 GMT 2012
993 
                     0x7ECE39DF
994 
                     generationID_3673615094
995
996
997 
                     ./ram_16x2k/implement/xst.scr
998 
                     ignore
999 
                     unknown
1000 
                     Wed Aug 08 21:16:29 GMT 2012
1001 
                     0x3885B366
1002 
                     generationID_3673615094
1003
1004
1005 
                     ./ram_16x2k/simulation/addr_gen.vhd
1006 
                     ignore
1007 
                     vhdl
1008 
                     Wed Aug 08 21:16:29 GMT 2012
1009 
                     0x886696A8
1010 
                     generationID_3673615094
1011
1012
1013 
                     ./ram_16x2k/simulation/bmg_stim_gen.vhd
1014 
                     ignore
1015 
                     vhdl
1016 
                     Wed Aug 08 21:16:29 GMT 2012
1017 
                     0x67B8D663
1018 
                     generationID_3673615094
1019
1020
1021 
                     ./ram_16x2k/simulation/bmg_tb_pkg.vhd
1022 
                     ignore
1023 
                     vhdl
1024 
                     Wed Aug 08 21:16:29 GMT 2012
1025 
                     0xD4F2B061
1026 
                     generationID_3673615094
1027
1028
1029 
                     ./ram_16x2k/simulation/checker.vhd
1030 
                     ignore
1031 
                     vhdl
1032 
                     Wed Aug 08 21:16:29 GMT 2012
1033 
                     0x2A8E7144
1034 
                     generationID_3673615094
1035
1036
1037 
                     ./ram_16x2k/simulation/data_gen.vhd
1038 
                     ignore
1039 
                     vhdl
1040 
                     Wed Aug 08 21:16:29 GMT 2012
1041 
                     0xE0759FCA
1042 
                     generationID_3673615094
1043
1044
1045 
                     ./ram_16x2k/simulation/functional/simcmds.tcl
1046 
                     ignore
1047 
                     tcl
1048 
                     Wed Aug 08 21:16:28 GMT 2012
1049 
                     0xE4C43C05
1050 
                     generationID_3673615094
1051
1052
1053 
                     ./ram_16x2k/simulation/functional/simulate_isim.sh
1054 
                     ignore
1055 
                     unknown
1056 
                     Wed Aug 08 21:16:29 GMT 2012
1057 
                     0x5A7547B8
1058 
                     generationID_3673615094
1059
1060
1061 
                     ./ram_16x2k/simulation/functional/simulate_mti.bat
1062 
                     ignore
1063 
                     unknown
1064 
                     Wed Aug 08 21:16:29 GMT 2012
1065 
                     0x86EA5D67
1066 
                     generationID_3673615094
1067
1068
1069 
                     ./ram_16x2k/simulation/functional/simulate_mti.do
1070 
                     ignore
1071 
                     unknown
1072 
                     Wed Aug 08 21:16:29 GMT 2012
1073 
                     0x70FC1A5A
1074 
                     generationID_3673615094
1075
1076
1077 
                     ./ram_16x2k/simulation/functional/simulate_mti.sh
1078 
                     ignore
1079 
                     unknown
1080 
                     Wed Aug 08 21:16:29 GMT 2012
1081 
                     0x86EA5D67
1082 
                     generationID_3673615094
1083
1084
1085 
                     ./ram_16x2k/simulation/functional/simulate_ncsim.sh
1086 
                     ignore
1087 
                     unknown
1088 
                     Wed Aug 08 21:16:28 GMT 2012
1089 
                     0xDFFAAD0B
1090 
                     generationID_3673615094
1091
1092
1093 
                     ./ram_16x2k/simulation/functional/simulate_vcs.sh
1094 
                     ignore
1095 
                     unknown
1096 
                     Wed Aug 08 21:16:28 GMT 2012
1097 
                     0x50F8DAD2
1098 
                     generationID_3673615094
1099
1100
1101 
                     ./ram_16x2k/simulation/functional/ucli_commands.key
1102 
                     ignore
1103 
                     unknown
1104 
                     Wed Aug 08 21:16:28 GMT 2012
1105 
                     0x7C0FA43B
1106 
                     generationID_3673615094
1107
1108
1109 
                     ./ram_16x2k/simulation/functional/vcs_session.tcl
1110 
                     ignore
1111 
                     tcl
1112 
                     Wed Aug 08 21:16:28 GMT 2012
1113 
                     0xD97735D5
1114 
                     generationID_3673615094
1115
1116
1117 
                     ./ram_16x2k/simulation/functional/wave_mti.do
1118 
                     ignore
1119 
                     unknown
1120 
                     Wed Aug 08 21:16:29 GMT 2012
1121 
                     0xE56F4D38
1122 
                     generationID_3673615094
1123
1124
1125 
                     ./ram_16x2k/simulation/functional/wave_ncsim.sv
1126 
                     ignore
1127 
                     unknown
1128 
                     Wed Aug 08 21:16:28 GMT 2012
1129 
                     0x10CE0A9D
1130 
                     generationID_3673615094
1131
1132
1133 
                     ./ram_16x2k/simulation/ram_16x2k_synth.vhd
1134 
                     ignore
1135 
                     vhdl
1136 
                     Wed Aug 08 21:16:29 GMT 2012
1137 
                     0xDD3B8E51
1138 
                     generationID_3673615094
1139
1140
1141 
                     ./ram_16x2k/simulation/ram_16x2k_tb.vhd
1142 
                     ignore
1143 
                     vhdl
1144 
                     Wed Aug 08 21:16:29 GMT 2012
1145 
                     0x183DC989
1146 
                     generationID_3673615094
1147
1148
1149 
                     ./ram_16x2k/simulation/random.vhd
1150 
                     ignore
1151 
                     vhdl
1152 
                     Wed Aug 08 21:16:29 GMT 2012
1153 
                     0xE1CDC376
1154 
                     generationID_3673615094
1155
1156
1157 
                     ./ram_16x2k/simulation/timing/simcmds.tcl
1158 
                     ignore
1159 
                     tcl
1160 
                     Wed Aug 08 21:16:28 GMT 2012
1161 
                     0xE4C43C05
1162 
                     generationID_3673615094
1163
1164
1165 
                     ./ram_16x2k/simulation/timing/simulate_isim.sh
1166 
                     ignore
1167 
                     unknown
1168 
                     Wed Aug 08 21:16:29 GMT 2012
1169 
                     0x76E29DB6
1170 
                     generationID_3673615094
1171
1172
1173 
                     ./ram_16x2k/simulation/timing/simulate_mti.bat
1174 
                     ignore
1175 
                     unknown
1176 
                     Wed Aug 08 21:16:29 GMT 2012
1177 
                     0x86EA5D67
1178 
                     generationID_3673615094
1179
1180
1181 
                     ./ram_16x2k/simulation/timing/simulate_mti.do
1182 
                     ignore
1183 
                     unknown
1184 
                     Wed Aug 08 21:16:29 GMT 2012
1185 
                     0xC49C06E1
1186 
                     generationID_3673615094
1187
1188
1189 
                     ./ram_16x2k/simulation/timing/simulate_mti.sh
1190 
                     ignore
1191 
                     unknown
1192 
                     Wed Aug 08 21:16:29 GMT 2012
1193 
                     0x86EA5D67
1194 
                     generationID_3673615094
1195
1196
1197 
                     ./ram_16x2k/simulation/timing/simulate_ncsim.sh
1198 
                     ignore
1199 
                     unknown
1200 
                     Wed Aug 08 21:16:28 GMT 2012
1201 
                     0x71C0CF92
1202 
                     generationID_3673615094
1203
1204
1205 
                     ./ram_16x2k/simulation/timing/simulate_vcs.sh
1206 
                     ignore
1207 
                     unknown
1208 
                     Wed Aug 08 21:16:28 GMT 2012
1209 
                     0xCC88418C
1210 
                     generationID_3673615094
1211
1212
1213 
                     ./ram_16x2k/simulation/timing/ucli_commands.key
1214 
                     ignore
1215 
                     unknown
1216 
                     Wed Aug 08 21:16:28 GMT 2012
1217 
                     0x7C0FA43B
1218 
                     generationID_3673615094
1219
1220
1221 
                     ./ram_16x2k/simulation/timing/vcs_session.tcl
1222 
                     ignore
1223 
                     tcl
1224 
                     Wed Aug 08 21:16:28 GMT 2012
1225 
                     0x3336849C
1226 
                     generationID_3673615094
1227
1228
1229 
                     ./ram_16x2k/simulation/timing/wave_mti.do
1230 
                     ignore
1231 
                     unknown
1232 
                     Wed Aug 08 21:16:29 GMT 2012
1233 
                     0x71C1D729
1234 
                     generationID_3673615094
1235
1236
1237 
                     ./ram_16x2k/simulation/timing/wave_ncsim.sv
1238 
                     ignore
1239 
                     unknown
1240 
                     Wed Aug 08 21:16:28 GMT 2012
1241 
                     0xCBFE8064
1242 
                     generationID_3673615094
1243
1244
1245
1246 
                  ngc_netlist_generator
1247
1248 
                     ./ram_16x2k.ngc
1249 
                     ngc
1250 
                     Wed Aug 08 21:17:18 GMT 2012
1251 
                     0xF5BAA26C
1252 
                     generationID_3673615094
1253
1254
1255
1256 
                  obfuscate_netlist_generator
1257
1258
1259 
                  padded_implementation_netlist_generator
1260
1261
1262 
                  instantiation_template_generator
1263
1264 
                     ./ram_16x2k.veo
1265 
                     veo
1266 
                     Wed Aug 08 21:17:18 GMT 2012
1267 
                     0x70458C57
1268 
                     generationID_3673615094
1269
1270
1271
1272 
                  synthesis_instantiation_wrapper_generator
1273
1274 
                     ./ram_16x2k_synth.v
1275 
                     verilog
1276 
                     verilogSynthesis
1277 
                     Wed Aug 08 21:17:18 GMT 2012
1278 
                     0x4B1216CF
1279 
                     generationID_3673615094
1280
1281
1282
1283 
                  structural_simulation_model_generator
1284
1285 
                     ./ram_16x2k.v
1286 
                     verilog
1287 
                     Wed Aug 08 21:17:19 GMT 2012
1288 
                     0xD73BAB65
1289 
                     generationID_3673615094
1290
1291
1292
1293 
                  all_documents_generator
1294
1295
1296 
                  asy_generator
1297
1298 
                     ./ram_16x2k.asy
1299 
                     asy
1300 
                     Wed Aug 08 21:17:22 GMT 2012
1301 
                     0xC9DF501E
1302 
                     generationID_3673615094
1303
1304
1305 
                     ./summary.log
1306 
                     unknown
1307 
                     Wed Aug 08 21:17:22 GMT 2012
1308 
                     0xE0AD8EEC
1309 
                     generationID_3673615094
1310
1311
1312
1313 
                  xmdf_generator
1314
1315 
                     ./ram_16x2k_xmdf.tcl
1316 
                     tclXmdf
1317 
                     tcl
1318 
                     Wed Aug 08 21:17:22 GMT 2012
1319 
                     0xF26FB160
1320 
                     generationID_3673615094
1321
1322
1323
1324 
                  synthesis_ise_generator
1325
1326 
                     ./ram_16x2k.gise
1327 
                     ignore
1328 
                     gise
1329 
                     Wed Aug 08 21:17:26 GMT 2012
1330 
                     0x78F752A5
1331 
                     generationID_3673615094
1332
1333
1334 
                     ./ram_16x2k.xise
1335 
                     ignore
1336 
                     xise
1337 
                     Wed Aug 08 21:17:26 GMT 2012
1338 
                     0x3D87F839
1339 
                     generationID_3673615094
1340
1341
1342
1343 
                  ise_generator
1344
1345 
                     ./ram_16x2k.gise
1346 
                     ignore
1347 
                     gise
1348 
                     Wed Aug 08 21:17:31 GMT 2012
1349 
                     0xE80C198E
1350 
                     generationID_3673615094
1351
1352
1353 
                     ./ram_16x2k.xise
1354 
                     ignore
1355 
                     xise
1356 
                     Wed Aug 08 21:17:31 GMT 2012
1357 
                     0xEA1827DB
1358 
                     generationID_3673615094
1359
1360
1361
1362 
                  deliver_readme_generator
1363
1364
1365 
                  flist_generator
1366
1367 
                     ./ram_16x2k_flist.txt
1368 
                     ignore
1369 
                     txtFlist
1370 
                     txt
1371 
                     Wed Aug 08 21:17:31 GMT 2012
1372 
                     0xA3FB9FC8
1373 
                     generationID_3673615094
1374
1375
1376
1377 
                  view_readme_generator
1378
1379
1380
1381
1382
1383
1384
1385
1386 
            coregen
1387 
            ./
1388 
            ./tmp/
1389 
            ./tmp/_cg/
1390
1391
1392 
            xc6slx9
1393 
            spartan6
1394 
            csg324
1395 
            -2
1396
1397
1398 
            BusFormatAngleBracketNotRipped
1399 
            Verilog
1400 
            true
1401 
            Foundation_ISE
1402 
            false
1403 
            false
1404 
            false
1405 
            Ngc
1406 
            false
1407
1408
1409 
            Behavioral
1410 
            Verilog
1411 
            false
1412
1413
1414
1415
1416 
 

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