OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [coregen.cgc] - Blame information for rev 167

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Line No. Rev Author Line
1 157 olivier.gi
2
3 
   xilinx.com
4 167 olivier.gi 
   project
5 157 olivier.gi 
   coregen
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   1.0
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         ram_16x1k_dp
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            ram_16x1k_dp
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            Native
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            AXI4_Full
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            Memory_Slave
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            false
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            True_Dual_Port_RAM
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            false
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            false
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            true
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            16
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            1024
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            16
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            WRITE_FIRST
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            Use_ENA_Pin
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            16
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            16
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            Use_ENB_Pin
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            no_coe_file_loaded
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            CE
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            CE
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            0
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            SYNC
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            false
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            100
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            50
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            100
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            50
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            100
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            100
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            ALL
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            false
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            false
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                  coregen
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                  ./
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                  ./tmp/
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                  ./tmp/_cg/
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                  xc6slx9
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                  spartan6
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                  csg324
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                  -2
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                  BusFormatAngleBracketNotRipped
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                  Verilog
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                  true
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                  Foundation_ISE
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                  false
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                  false
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                  false
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                  Ngc
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                  false
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                  Behavioral
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                  Verilog
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                  false
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                  2012-06-25+21:54
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         ram_16x1k_sp
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            ram_16x1k_sp
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            Native
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            AXI4_Full
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            Memory_Slave
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            false
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            4
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            Single_Port_RAM
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            false
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            No_ECC
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            false
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            false
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            false
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            Single_Bit_Error_Injection
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            true
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            8
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            Minimum_Area
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            8kx2
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            false
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            16
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            1024
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            16
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            WRITE_FIRST
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            Use_ENA_Pin
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            WRITE_FIRST
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            Always_Enabled
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            false
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            false
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            false
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            false
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            false
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            false
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            0
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            false
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            no_coe_file_loaded
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            false
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            0
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            false
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            false
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            CE
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            0
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            false
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            false
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            CE
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            0
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            SYNC
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            false
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            100
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            50
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            0
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            0
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            100
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            0
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            ALL
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            false
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            false
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                  coregen
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                  ./
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                  ./tmp/
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                  ./tmp/_cg/
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                  xc6slx9
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                  spartan6
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                  csg324
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                  -2
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                  BusFormatAngleBracketNotRipped
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                  Verilog
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                  true
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                  Foundation_ISE
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                  false
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                  false
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                  false
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                  Ngc
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                  false
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                  Behavioral
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                  Verilog
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                  false
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                  2012-06-25+21:54
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         ram_16x8k_dp
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            ram_16x8k_dp
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            Native
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            AXI4_Full
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            Memory_Slave
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            false
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            4
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            True_Dual_Port_RAM
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            false
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            No_ECC
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            false
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            false
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            false
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            Single_Bit_Error_Injection
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            true
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            8
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            Minimum_Area
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            8kx2
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            true
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            16
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            8192
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            16
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            WRITE_FIRST
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            Use_ENA_Pin
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            16
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            16
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            WRITE_FIRST
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            Use_ENB_Pin
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            false
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            false
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            false
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            false
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            false
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            false
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            false
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            false
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            0
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            false
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            no_coe_file_loaded
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            false
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            0
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            false
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            false
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            CE
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            0
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            false
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            false
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            CE
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            0
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            SYNC
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            false
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            100
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            50
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            100
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            50
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            100
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            100
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            ALL
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            false
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            false
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            spartan6
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            spartan6
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            /home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/tmp/_cg/
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            0
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            1
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            0
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            0
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            4
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            2
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            8
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            1
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            1
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            0
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            no_coe_file_loaded
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            0
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            0
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            SYNC
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            0
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            CE
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            0
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            0
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            1
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            0
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            1
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            2
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            WRITE_FIRST
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            16
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            16
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            8192
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            8192
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            13
302 157 olivier.gi 
            0
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            CE
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            0
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            0
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            1
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            0
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            1
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            2
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            WRITE_FIRST
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            16
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            16
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            8192
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            8192
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            13
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            0
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            ALL
327 167 olivier.gi 
            1
328 157 olivier.gi 
            0
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            0
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            0
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333 167 olivier.gi
334 157 olivier.gi
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                  coregen
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                  ./
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                  ./tmp/
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                  ./tmp/_cg/
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                  xc6slx9
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                  spartan6
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                  csg324
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                  -2
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                  BusFormatAngleBracketNotRipped
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                  Verilog
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                  true
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                  Foundation_ISE
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                  false
352 
                  false
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                  false
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                  Ngc
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                  false
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                  Behavioral
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                  Verilog
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                  false
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                  2012-06-25+21:54
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                  customization_generator
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                     ./summary.log
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                     unknown
372 167 olivier.gi 
                     Fri Nov 30 22:43:36 GMT 2012
373 
                     0x76A61D5C
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                     generationID_4013899584
375 157 olivier.gi
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                  model_parameter_resolution_generator
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                     ./summary.log
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                     unknown
382 167 olivier.gi 
                     Fri Nov 30 22:43:41 GMT 2012
383 
                     0x76A61D5C
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                     generationID_4013899584
385 157 olivier.gi
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                  ip_xco_generator
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390 167 olivier.gi 
                     ./ram_16x8k_dp.xco
391 157 olivier.gi 
                     xco
392 167 olivier.gi 
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                     0xBCE8DABB
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                     generationID_4013899584
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                  associated_files_generator
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400 167 olivier.gi 
                     ./ram_16x8k_dp/blk_mem_gen_v7_2_readme.txt
401 157 olivier.gi 
                     ignore
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                     txt
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                     0x5661B352
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                     ./ram_16x8k_dp/doc/blk_mem_gen_v7_2_vinfo.html
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                     ignore
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                     unknown
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                     Sat Jul 21 06:10:41 GMT 2012
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                     0x4D7A616C
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                     generationID_4013899584
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416 167 olivier.gi 
                     ./ram_16x8k_dp/doc/pg058-blk-mem-gen.pdf
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                     ignore
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                     pdf
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                     Sat Jul 21 06:10:41 GMT 2012
420 
                     0xAE5E57E0
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                     generationID_4013899584
422 157 olivier.gi
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                  ejava_generator
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427 167 olivier.gi 
                     ./ram_16x8k_dp/example_design/ram_16x8k_dp_exdes.ucf
428 157 olivier.gi 
                     ignore
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                     ucf
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431 
                     0x8915DFA1
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                     generationID_4013899584
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                     ./ram_16x8k_dp/example_design/ram_16x8k_dp_exdes.vhd
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                     ignore
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                     vhdl
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                     generationID_4013899584
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443 167 olivier.gi 
                     ./ram_16x8k_dp/example_design/ram_16x8k_dp_exdes.xdc
444 157 olivier.gi 
                     ignore
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                     xdc
446 167 olivier.gi 
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447 
                     0x78E2D49A
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                     generationID_4013899584
449 157 olivier.gi
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451 167 olivier.gi 
                     ./ram_16x8k_dp/example_design/ram_16x8k_dp_prod.vhd
452 157 olivier.gi 
                     ignore
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                     vhdl
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                     0x438ACD9E
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                     generationID_4013899584
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459 167 olivier.gi 
                     ./ram_16x8k_dp/implement/implement.bat
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                     ignore
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                     unknown
462 167 olivier.gi 
                     Fri Nov 30 22:43:43 GMT 2012
463 
                     0xB9217A9D
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                     generationID_4013899584
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467 167 olivier.gi 
                     ./ram_16x8k_dp/implement/implement.sh
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                     ignore
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471 
                     0xAF7804B8
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                     generationID_4013899584
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                     ./ram_16x8k_dp/implement/planAhead_ise.bat
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                     ignore
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                     0x45F8EA6E
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                     ./ram_16x8k_dp/implement/planAhead_ise.sh
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                     ignore
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                     0x2D190EC7
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                     generationID_4013899584
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                     ./ram_16x8k_dp/implement/planAhead_ise.tcl
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                     ignore
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                     tcl
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                     0x5D0CC17F
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                     generationID_4013899584
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                     ./ram_16x8k_dp/implement/xst.prj
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                     ignore
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                     0x95A3A394
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                     generationID_4013899584
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                     ./ram_16x8k_dp/implement/xst.scr
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                     ignore
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                     0xAEFDBD03
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                     ./ram_16x8k_dp/simulation/addr_gen.vhd
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                     ignore
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                     vhdl
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                     ./ram_16x8k_dp/simulation/bmg_stim_gen.vhd
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                     ignore
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                     vhdl
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                     generationID_4013899584
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                     ./ram_16x8k_dp/simulation/bmg_tb_pkg.vhd
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                     ignore
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                     vhdl
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                     ./ram_16x8k_dp/simulation/checker.vhd
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                     vhdl
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                     ./ram_16x8k_dp/simulation/data_gen.vhd
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                     ./ram_16x8k_dp/simulation/functional/simcmds.tcl
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                     tcl
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                     ./ram_16x8k_dp/simulation/functional/simulate_isim.sh
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                     ignore
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                     ./ram_16x8k_dp/simulation/functional/simulate_mti.bat
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579 167 olivier.gi 
                     ./ram_16x8k_dp/simulation/functional/simulate_mti.do
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                     ./ram_16x8k_dp/simulation/functional/simulate_mti.sh
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                     ./ram_16x8k_dp/simulation/functional/simulate_ncsim.sh
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                     ./ram_16x8k_dp/simulation/functional/simulate_vcs.sh
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                     ./ram_16x8k_dp/simulation/functional/ucli_commands.key
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                     ./ram_16x8k_dp/simulation/functional/vcs_session.tcl
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                     ./ram_16x8k_dp/simulation/functional/wave_mti.do
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                     ./ram_16x8k_dp/simulation/functional/wave_ncsim.sv
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                     ./ram_16x8k_dp/simulation/ram_16x8k_dp_synth.vhd
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                     ./ram_16x8k_dp/simulation/ram_16x8k_dp_tb.vhd
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                     ./ram_16x8k_dp/simulation/timing/simcmds.tcl
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                     ./ram_16x8k_dp/simulation/timing/simulate_mti.bat
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                     ./ram_16x8k_dp/simulation/timing/simulate_mti.do
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                     ./ram_16x8k_dp/simulation/timing/simulate_ncsim.sh
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                     ./ram_16x8k_dp/simulation/timing/simulate_vcs.sh
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                     ./ram_16x8k_dp/simulation/timing/ucli_commands.key
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                     Fri Nov 30 22:43:42 GMT 2012
727 
                     0xCF9470F3
728 
                     generationID_4013899584
729 157 olivier.gi
730
731 167 olivier.gi 
                     ./ram_16x8k_dp/simulation/timing/vcs_session.tcl
732 157 olivier.gi 
                     ignore
733 
                     tcl
734 167 olivier.gi 
                     Fri Nov 30 22:43:42 GMT 2012
735 
                     0x8B5C0EEA
736 
                     generationID_4013899584
737 157 olivier.gi
738
739 167 olivier.gi 
                     ./ram_16x8k_dp/simulation/timing/wave_mti.do
740 157 olivier.gi 
                     ignore
741 
                     unknown
742 167 olivier.gi 
                     Fri Nov 30 22:43:43 GMT 2012
743 
                     0xA057B0F6
744 
                     generationID_4013899584
745 157 olivier.gi
746
747 167 olivier.gi 
                     ./ram_16x8k_dp/simulation/timing/wave_ncsim.sv
748 157 olivier.gi 
                     ignore
749 
                     unknown
750 167 olivier.gi 
                     Fri Nov 30 22:43:42 GMT 2012
751 
                     0xF50DC3A6
752 
                     generationID_4013899584
753 157 olivier.gi
754
755
756 
                  ngc_netlist_generator
757
758 167 olivier.gi 
                     ./ram_16x8k_dp.ngc
759 157 olivier.gi 
                     ngc
760 167 olivier.gi 
                     Fri Nov 30 22:44:40 GMT 2012
761 
                     0xC275AA7D
762 
                     generationID_4013899584
763 157 olivier.gi
764
765
766 
                  obfuscate_netlist_generator
767
768
769 
                  padded_implementation_netlist_generator
770
771
772 
                  instantiation_template_generator
773
774 167 olivier.gi 
                     ./ram_16x8k_dp.veo
775 157 olivier.gi 
                     veo
776 167 olivier.gi 
                     Fri Nov 30 22:44:40 GMT 2012
777 
                     0x44743D78
778 
                     generationID_4013899584
779 157 olivier.gi
780
781
782 
                  synthesis_instantiation_wrapper_generator
783
784 167 olivier.gi 
                     ./ram_16x8k_dp_synth.v
785 157 olivier.gi 
                     verilog
786 
                     verilogSynthesis
787 167 olivier.gi 
                     Fri Nov 30 22:44:40 GMT 2012
788 
                     0xC56A17C4
789 
                     generationID_4013899584
790 157 olivier.gi
791
792
793 
                  structural_simulation_model_generator
794
795 167 olivier.gi 
                     ./ram_16x8k_dp.v
796 157 olivier.gi 
                     verilog
797 167 olivier.gi 
                     Fri Nov 30 22:44:40 GMT 2012
798 
                     0xA580F986
799 
                     generationID_4013899584
800 157 olivier.gi
801
802
803 
                  all_documents_generator
804
805
806 
                  asy_generator
807
808 167 olivier.gi 
                     ./ram_16x8k_dp.asy
809 157 olivier.gi 
                     asy
810 167 olivier.gi 
                     Fri Nov 30 22:44:44 GMT 2012
811 
                     0xC80F28A5
812 
                     generationID_4013899584
813 157 olivier.gi
814
815 
                     ./summary.log
816 
                     unknown
817 167 olivier.gi 
                     Fri Nov 30 22:44:44 GMT 2012
818 
                     0x76A61D5C
819 
                     generationID_4013899584
820 157 olivier.gi
821
822
823 
                  xmdf_generator
824
825 167 olivier.gi 
                     ./ram_16x8k_dp_xmdf.tcl
826 157 olivier.gi 
                     tclXmdf
827 
                     tcl
828 167 olivier.gi 
                     Fri Nov 30 22:44:44 GMT 2012
829 
                     0xB7CBC7A4
830 
                     generationID_4013899584
831 157 olivier.gi
832
833
834 
                  synthesis_ise_generator
835
836 167 olivier.gi 
                     ./ram_16x8k_dp.gise
837 157 olivier.gi 
                     ignore
838 
                     gise
839 167 olivier.gi 
                     Fri Nov 30 22:44:51 GMT 2012
840 
                     0x552D948D
841 
                     generationID_4013899584
842 157 olivier.gi
843
844 167 olivier.gi 
                     ./ram_16x8k_dp.xise
845 157 olivier.gi 
                     ignore
846 
                     xise
847 167 olivier.gi 
                     Fri Nov 30 22:44:51 GMT 2012
848 
                     0x46AD741A
849 
                     generationID_4013899584
850 157 olivier.gi
851
852
853 
                  ise_generator
854
855 167 olivier.gi 
                     ./ram_16x8k_dp.gise
856 157 olivier.gi 
                     ignore
857 
                     gise
858 167 olivier.gi 
                     Fri Nov 30 22:44:55 GMT 2012
859 
                     0x54560CD3
860 
                     generationID_4013899584
861 157 olivier.gi
862
863 167 olivier.gi 
                     ./ram_16x8k_dp.xise
864 157 olivier.gi 
                     ignore
865 
                     xise
866 167 olivier.gi 
                     Fri Nov 30 22:44:55 GMT 2012
867 
                     0x30454A9B
868 
                     generationID_4013899584
869 157 olivier.gi
870
871
872 
                  deliver_readme_generator
873
874
875 
                  flist_generator
876
877 167 olivier.gi 
                     ./ram_16x8k_dp_flist.txt
878 157 olivier.gi 
                     ignore
879 
                     txtFlist
880 
                     txt
881 167 olivier.gi 
                     Fri Nov 30 22:44:55 GMT 2012
882 
                     0x53BF6150
883 
                     generationID_4013899584
884 157 olivier.gi
885
886
887 
                  view_readme_generator
888
889
890
891
892 167 olivier.gi
893 
         ram_16x4k_dp
894
895
896 
            ram_16x4k_dp
897 
            Native
898 
            AXI4_Full
899 
            Memory_Slave
900 
            false
901 
            4
902 
            True_Dual_Port_RAM
903 
            false
904 
            No_ECC
905 
            false
906 
            false
907 
            false
908 
            Single_Bit_Error_Injection
909 
            true
910 
            8
911 
            Minimum_Area
912 
            8kx2
913 
            true
914 
            16
915 
            4096
916 
            16
917 
            WRITE_FIRST
918 
            Use_ENA_Pin
919 
            16
920 
            16
921 
            WRITE_FIRST
922 
            Use_ENB_Pin
923 
            false
924 
            false
925 
            false
926 
            false
927 
            false
928 
            false
929 
            false
930 
            false
931 
            0
932 
            false
933 
            no_coe_file_loaded
934 
            false
935 
            0
936 
            false
937 
            false
938 
            CE
939 
            0
940 
            false
941 
            false
942 
            CE
943 
            0
944 
            SYNC
945 
            false
946 
            100
947 
            50
948 
            100
949 
            50
950 
            100
951 
            100
952 
            ALL
953 
            false
954 
            false
955
956
957
958
959 
                  coregen
960 
                  ./
961 
                  ./tmp/
962 
                  ./tmp/_cg/
963
964
965 
                  xc6slx9
966 
                  spartan6
967 
                  csg324
968 
                  -2
969
970
971 
                  BusFormatAngleBracketNotRipped
972 
                  Verilog
973 
                  true
974 
                  Foundation_ISE
975 
                  false
976 
                  false
977 
                  false
978 
                  Ngc
979 
                  false
980
981
982 
                  Behavioral
983 
                  Verilog
984 
                  false
985
986
987 
                  2012-06-25+21:54
988
989
990
991
992 157 olivier.gi
993
994
995
996 
            coregen
997 
            ./
998 
            ./tmp/
999 
            ./tmp/_cg/
1000
1001
1002 
            xc6slx9
1003 
            spartan6
1004 
            csg324
1005 
            -2
1006
1007
1008 
            BusFormatAngleBracketNotRipped
1009 
            Verilog
1010 
            true
1011 
            Foundation_ISE
1012 
            false
1013 
            false
1014 
            false
1015 
            Ngc
1016 
            false
1017
1018
1019 
            Behavioral
1020 
            Verilog
1021 
            false
1022
1023
1024
1025
1026 
 

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