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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [coregen.cgp] - Blame information for rev 213

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# Date: Wed Aug  8 21:13:06 2012
 
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = ./tmp/
 
# CRC:  2347c56

Line No.	Rev	Author	Line
1	157	olivier.gi	`# Date: Wed Aug 8 21:13:06 2012`
2
3			`SET addpads = false`
4			`SET asysymbol = true`
5			`SET busformat = BusFormatAngleBracketNotRipped`
6			`SET createndf = false`
7			`SET designentry = Verilog`
8			`SET device = xc6slx9`
9			`SET devicefamily = spartan6`
10			`SET flowvendor = Foundation_ISE`
11			`SET formalverification = false`
12			`SET foundationsym = false`
13			`SET implementationfiletype = Ngc`
14			`SET package = csg324`
15			`SET removerpms = false`
16			`SET simulationfiles = Behavioral`
17			`SET speedgrade = -2`
18			`SET verilogsim = true`
19			`SET vhdlsim = false`
20			`SET workingdirectory = ./tmp/`
21
22			`# CRC: 2347c56`

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [coregen.cgp] - Blame information for rev 213