| 1 |
157 |
olivier.gi |
Welcome to Xilinx CORE Generator.
|
| 2 |
|
|
Help system initialized.
|
| 3 |
|
|
The IP Catalog has been reloaded.
|
| 4 |
167 |
olivier.gi |
Opening project file
|
| 5 |
|
|
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
|
| 6 |
|
|
log/coregen/coregen.cgp.
|
| 7 |
|
|
Recustomize and Generate (Under Original Project Settings)INFO:sim:172 - Generating IP...
|
| 8 |
|
|
Resolving generics for 'ram_16x8k_dp'...
|
| 9 |
|
|
Applying external generics to 'ram_16x8k_dp'...
|
| 10 |
|
|
Delivering associated files for 'ram_16x8k_dp'...
|
| 11 |
157 |
olivier.gi |
WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
|
| 12 |
|
|
Verilog synthesis
|
| 13 |
167 |
olivier.gi |
Delivering EJava files for 'ram_16x8k_dp'...
|
| 14 |
|
|
Generating implementation netlist for 'ram_16x8k_dp'...
|
| 15 |
|
|
INFO:sim - Pre-processing HDL files for 'ram_16x8k_dp'...
|
| 16 |
|
|
Running synthesis for 'ram_16x8k_dp'
|
| 17 |
157 |
olivier.gi |
Running ngcbuild...
|
| 18 |
167 |
olivier.gi |
Writing VEO instantiation template for 'ram_16x8k_dp'...
|
| 19 |
|
|
Writing Verilog instantiation wrapper for 'ram_16x8k_dp'...
|
| 20 |
|
|
Writing Verilog behavioral simulation model for 'ram_16x8k_dp'...
|
| 21 |
157 |
olivier.gi |
WARNING:sim - No files were found for the view xilinx_documentation
|
| 22 |
|
|
Generating ASY schematic symbol...
|
| 23 |
|
|
INFO:sim:949 - Finished generation of ASY schematic symbol.
|
| 24 |
|
|
Generating metadata file...
|
| 25 |
167 |
olivier.gi |
Generating ISE project file for 'ram_16x8k_dp'...
|
| 26 |
157 |
olivier.gi |
Generating ISE project...
|
| 27 |
167 |
olivier.gi |
XCO file found: ram_16x8k_dp.xco
|
| 28 |
|
|
XMDF file found: ram_16x8k_dp_xmdf.tcl
|
| 29 |
157 |
olivier.gi |
Adding
|
| 30 |
167 |
olivier.gi |
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
|
| 31 |
|
|
log/coregen/tmp/_cg/ram_16x8k_dp.asy -view all -origin_type imported
|
| 32 |
157 |
olivier.gi |
Adding
|
| 33 |
167 |
olivier.gi |
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
|
| 34 |
|
|
log/coregen/tmp/_cg/ram_16x8k_dp.ngc -view all -origin_type created
|
| 35 |
157 |
olivier.gi |
Checking file
|
| 36 |
167 |
olivier.gi |
"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/ver
|
| 37 |
|
|
ilog/coregen/tmp/_cg/ram_16x8k_dp.ngc" for project device match ...
|
| 38 |
157 |
olivier.gi |
File
|
| 39 |
167 |
olivier.gi |
"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/ver
|
| 40 |
|
|
ilog/coregen/tmp/_cg/ram_16x8k_dp.ngc" device information matches project
|
| 41 |
|
|
device.
|
| 42 |
157 |
olivier.gi |
Adding
|
| 43 |
167 |
olivier.gi |
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
|
| 44 |
|
|
log/coregen/tmp/_cg/ram_16x8k_dp.v -view all -origin_type created
|
| 45 |
157 |
olivier.gi |
INFO:HDLCompiler:1845 - Analyzing Verilog file
|
| 46 |
167 |
olivier.gi |
"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/
|
| 47 |
|
|
verilog/coregen/tmp/_cg/ram_16x8k_dp.v" into library work
|
| 48 |
157 |
olivier.gi |
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
|
| 49 |
|
|
Adding
|
| 50 |
167 |
olivier.gi |
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
|
| 51 |
|
|
log/coregen/tmp/_cg/ram_16x8k_dp.veo -view all -origin_type imported
|
| 52 |
157 |
olivier.gi |
Adding
|
| 53 |
167 |
olivier.gi |
/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/veri
|
| 54 |
|
|
log/coregen/tmp/_cg/ram_16x8k_dp_synth.v -view all -origin_type created
|
| 55 |
157 |
olivier.gi |
INFO:HDLCompiler:1845 - Analyzing Verilog file
|
| 56 |
167 |
olivier.gi |
"/home/pitchu/Projects/verilog/openMSP430/fpga/xilinx_avnet_lx9microbard/rtl/
|
| 57 |
|
|
verilog/coregen/tmp/_cg/ram_16x8k_dp_synth.v" into library work
|
| 58 |
157 |
olivier.gi |
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
|
| 59 |
|
|
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
|
| 60 |
|
|
Please set the new top explicitly by running the "project set top" command.
|
| 61 |
|
|
To re-calculate the new top automatically, set the "Auto Implementation Top"
|
| 62 |
|
|
property to true.
|
| 63 |
167 |
olivier.gi |
Top level has been set to "/ram_16x8k_dp"
|
| 64 |
157 |
olivier.gi |
Generating README file...
|
| 65 |
|
|
Generating FLIST file...
|
| 66 |
|
|
INFO:sim:948 - Finished FLIST file generation.
|
| 67 |
|
|
Launching README viewer...
|
| 68 |
|
|
Moving files to output directory...
|
| 69 |
|
|
Finished moving files to output directory
|
| 70 |
|
|
Saved CGP file for project 'coregen'.
|
| 71 |
|
|
Closed project file.
|
