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--

-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench

--

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-- Filename: ram_16x1k_dp_tb.vhd

-- Description:

--  Testbench Top

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-- Author: IP Solutions Division

--

-- History: Sep 12, 2011 - First Release

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--

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-- Library Declarations

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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY work;

USE work.ALL;

ENTITY ram_16x1k_dp_tb IS

END ENTITY;

ARCHITECTURE ram_16x1k_dp_tb_ARCH OF ram_16x1k_dp_tb IS

 SIGNAL  STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);

 SIGNAL  CLK :  STD_LOGIC := '1';

 SIGNAL  CLKB :  STD_LOGIC := '1';

 SIGNAL  RESET : STD_LOGIC;

 BEGIN

 CLK_GEN: PROCESS BEGIN

     CLK <= NOT CLK;

     WAIT FOR 100 NS;

     CLK <= NOT CLK;

     WAIT FOR 100 NS;

  END PROCESS;

 CLKB_GEN: PROCESS BEGIN

     CLKB <= NOT CLKB;

     WAIT FOR 100 NS;

     CLKB <= NOT CLKB;

     WAIT FOR 100 NS;

  END PROCESS;

  RST_GEN: PROCESS BEGIN

    RESET <= '1';

    WAIT FOR 1000 NS;

    RESET <= '0';

    WAIT;

  END PROCESS;

--STOP_SIM: PROCESS BEGIN

-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS

--   ASSERT FALSE

--     REPORT "END SIMULATION TIME REACHED"

--     SEVERITY FAILURE;

--END PROCESS;

--

PROCESS BEGIN

  WAIT UNTIL STATUS(8)='1';

  IF( STATUS(7 downto 0)/="0") THEN

    ASSERT false

     REPORT "Simulation Failed"

         SEVERITY FAILURE;

  ELSE

   ASSERT false

     REPORT "Test Completed Successfully"

         SEVERITY FAILURE;

  END IF;

END PROCESS;

  ram_16x1k_dp_synth_inst:ENTITY work.ram_16x1k_dp_synth

  PORT MAP(

           CLK_IN   => CLK,

           CLKB_IN   => CLK,

           RESET_IN => RESET,

           STATUS   => STATUS

          );

END ARCHITECTURE;