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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_dp.asy] - Blame information for rev 167

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Line No. Rev Author Line
1 167 olivier.gi 
Version 4
2 
SymbolType BLOCK
3 
TEXT 32 32 LEFT 4 ram_16x1k_dp
4 
RECTANGLE Normal 32 32 544 1376
5 
LINE Wide 0 80 32 80
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PIN 0 80 LEFT 36
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PINATTR PinName addra[9:0]
8 
PINATTR Polarity IN
9 
LINE Wide 0 112 32 112
10 
PIN 0 112 LEFT 36
11 
PINATTR PinName dina[15:0]
12 
PINATTR Polarity IN
13 
LINE Normal 0 144 32 144
14 
PIN 0 144 LEFT 36
15 
PINATTR PinName ena
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PINATTR Polarity IN
17 
LINE Wide 0 208 32 208
18 
PIN 0 208 LEFT 36
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PINATTR PinName wea[1:0]
20 
PINATTR Polarity IN
21 
LINE Normal 0 272 32 272
22 
PIN 0 272 LEFT 36
23 
PINATTR PinName clka
24 
PINATTR Polarity IN
25 
LINE Wide 0 432 32 432
26 
PIN 0 432 LEFT 36
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PINATTR PinName addrb[9:0]
28 
PINATTR Polarity IN
29 
LINE Wide 0 464 32 464
30 
PIN 0 464 LEFT 36
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PINATTR PinName dinb[15:0]
32 
PINATTR Polarity IN
33 
LINE Normal 0 496 32 496
34 
PIN 0 496 LEFT 36
35 
PINATTR PinName enb
36 
PINATTR Polarity IN
37 
LINE Wide 0 560 32 560
38 
PIN 0 560 LEFT 36
39 
PINATTR PinName web[1:0]
40 
PINATTR Polarity IN
41 
LINE Normal 0 624 32 624
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PIN 0 624 LEFT 36
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PINATTR PinName clkb
44 
PINATTR Polarity IN
45 
LINE Wide 576 80 544 80
46 
PIN 576 80 RIGHT 36
47 
PINATTR PinName douta[15:0]
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PINATTR Polarity OUT
49 
LINE Wide 576 368 544 368
50 
PIN 576 368 RIGHT 36
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PINATTR PinName doutb[15:0]
52 
PINATTR Polarity OUT
53 
 

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