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olivier.gi |
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used solely *
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* for design, simulation, implementation and creation of design files *
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* limited to Xilinx devices or technologies. Use with non-Xilinx *
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* devices or technologies is expressly prohibited and immediately *
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* terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
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* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
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* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
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* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
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* PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support appliances, *
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* devices, or systems. Use in such applications are expressly *
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* prohibited. *
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* *
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* (c) Copyright 1995-2012 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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/*******************************************************************************
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* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 *
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* *
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* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
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* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
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* direct drop-in replacement. It should be used in all new Xilinx *
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* designs. The core supports RAM and ROM functions over a wide range of *
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* widths and depths. Use this core to generate block memories with *
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* symmetric or asymmetric read and write port widths, as well as cores *
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* which can perform simultaneous write operations to separate *
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* locations, and simultaneous read operations from the same location. *
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* For more information on differences in interface and feature support *
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* between this core and the Dual Port Block Memory and Single Port *
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* Block Memory LogiCOREs, please consult the data sheet. *
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*******************************************************************************/
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// Synthesized Netlist Wrapper
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// This file is provided to wrap around the synthesized netlist (if appropriate)
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// Interfaces:
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// CLK.ACLK
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// AXI4 Interconnect Clock Input
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// RST.ARESETN
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// AXI4 Interconnect Reset Input
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// AXI_SLAVE_S_AXI
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// AXI_SLAVE
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// AXILite_SLAVE_S_AXI
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// AXILite_SLAVE
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// BRAM_PORTA
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// BRAM_PORTA
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// BRAM_PORTB
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// BRAM_PORTB
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module ram_16x1k_dp (
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clka,
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ena,
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wea,
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addra,
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dina,
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douta,
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clkb,
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enb,
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web,
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addrb,
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dinb,
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doutb
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);
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input clka;
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input ena;
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input [1 : 0] wea;
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input [9 : 0] addra;
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input [15 : 0] dina;
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output [15 : 0] douta;
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input clkb;
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input enb;
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input [1 : 0] web;
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input [9 : 0] addrb;
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input [15 : 0] dinb;
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output [15 : 0] doutb;
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// WARNING: This file provides a module declaration only, it does not support
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// direct instantiation. Please use an instantiation template (VEO) to
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// instantiate the IP within a design.
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endmodule
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