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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_sp.asy] - Blame information for rev 171

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Line No. Rev Author Line
1 167 olivier.gi 
Version 4
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SymbolType BLOCK
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TEXT 32 32 LEFT 4 ram_16x1k_sp
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RECTANGLE Normal 32 32 544 1376
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LINE Wide 0 80 32 80
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PIN 0 80 LEFT 36
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PINATTR PinName addra[9:0]
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PINATTR Polarity IN
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LINE Wide 0 112 32 112
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PIN 0 112 LEFT 36
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PINATTR PinName dina[15:0]
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PINATTR Polarity IN
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LINE Normal 0 144 32 144
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PIN 0 144 LEFT 36
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PINATTR PinName ena
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PINATTR Polarity IN
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LINE Wide 0 208 32 208
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PIN 0 208 LEFT 36
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PINATTR PinName wea[1:0]
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PINATTR Polarity IN
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LINE Normal 0 272 32 272
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PIN 0 272 LEFT 36
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PINATTR PinName clka
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PINATTR Polarity IN
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LINE Wide 576 80 544 80
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PIN 576 80 RIGHT 36
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PINATTR PinName douta[15:0]
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PINATTR Polarity OUT
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