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--

-- BLK MEM GEN v7.1 Core - Top-level core wrapper

--

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--

-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.

--

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

--

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--

-- Filename: ram_16x8k_dp_exdes.vhd

--

-- Description:

--   This is the actual BMG core wrapper.

--

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-- Author: IP Solutions Division

--

-- History: August 31, 2005 - First Release

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--

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-- Library Declarations

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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY UNISIM;

USE UNISIM.VCOMPONENTS.ALL;

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-- Entity Declaration

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ENTITY ram_16x8k_dp_exdes IS

  PORT (

      --Inputs - Port A

    ENA            : IN STD_LOGIC;  --opt port

    WEA            : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);

    DINA           : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

    DOUTA          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    CLKA       : IN STD_LOGIC;

      --Inputs - Port B

    ENB            : IN STD_LOGIC;  --opt port

    WEB            : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

    ADDRB          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);

    DINB           : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

    DOUTB          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    CLKB           : IN STD_LOGIC

  );

END ram_16x8k_dp_exdes;

ARCHITECTURE xilinx OF ram_16x8k_dp_exdes IS

  COMPONENT BUFG IS

  PORT (

     I      : IN STD_ULOGIC;

     O      : OUT STD_ULOGIC

  );

  END COMPONENT;

  COMPONENT ram_16x8k_dp IS

  PORT (

      --Port A

    ENA        : IN STD_LOGIC;  --opt port

    WEA        : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

    ADDRA      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);

    DINA       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

    DOUTA      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    CLKA       : IN STD_LOGIC;

      --Port B

    ENB        : IN STD_LOGIC;  --opt port

    WEB        : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

    ADDRB      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);

    DINB       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

    DOUTB      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

    CLKB       : IN STD_LOGIC

  );

  END COMPONENT;

  SIGNAL CLKA_buf     : STD_LOGIC;

  SIGNAL CLKB_buf     : STD_LOGIC;

  SIGNAL S_ACLK_buf   : STD_LOGIC;

BEGIN

  bufg_A : BUFG

    PORT MAP (

     I => CLKA,

     O => CLKA_buf

     );

  bufg_B : BUFG

    PORT MAP (

     I => CLKB,

     O => CLKB_buf

     );

  bmg0 : ram_16x8k_dp

    PORT MAP (

      --Port A

      ENA        => ENA,

      WEA        => WEA,

      ADDRA      => ADDRA,

      DINA       => DINA,

      DOUTA      => DOUTA,

      CLKA       => CLKA_buf,

      --Port B

      ENB        => ENB,

      WEB        => WEB,

      ADDRB      => ADDRB,

      DINB       => DINB,

      DOUTB      => DOUTB,

      CLKB       => CLKB_buf

    );

END xilinx;