URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x8k_dp/] [implement/] [xst.scr] - Blame information for rev 167

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run
-ifmt VHDL
-ent ram_16x8k_dp_exdes
-p xc6slx9-csg324-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn ram_16x8k_dp_exdes
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain

Line No.	Rev	Author	Line
1	167	olivier.gi	`run`
2			`-ifmt VHDL`
3			`-ent ram_16x8k_dp_exdes`
4			`-p xc6slx9-csg324-2`
5			`-ifn xst.prj`
6			`-write_timing_constraints No`
7			`-iobuf YES`
8			`-max_fanout 100`
9			`-ofn ram_16x8k_dp_exdes`
10			`-ofmt NGC`
11			`-bus_delimiter ()`
12			`-hierarchy_separator /`
13			`-case Maintain`

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x8k_dp/] [implement/] [xst.scr] - Blame information for rev 167