URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x8k_dp/] [simulation/] [timing/] [wave_mti.do] - Blame information for rev 167

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onerror {resume}
quietly WaveActivateNextPane {} 0
 
 
      add wave -noupdate /ram_16x8k_dp_tb/status
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/CLKA
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ADDRA
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DINA
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/WEA
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ENA
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DOUTA
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/CLKB
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ADDRB
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ENB
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DINB
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/WEB
      add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DOUTB
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {9464063 ps}

Line No.	Rev	Author	Line
1	167	olivier.gi
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9			`onerror {resume}`
10			`quietly WaveActivateNextPane {} 0`
11
12
13			`add wave -noupdate /ram_16x8k_dp_tb/status`
14			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/CLKA`
15			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ADDRA`
16			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DINA`
17			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/WEA`
18			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ENA`
19			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DOUTA`
20			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/CLKB`
21			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ADDRB`
22			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/ENB`
23			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DINB`
24			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/WEB`
25			`add wave -noupdate /ram_16x8k_dp_tb/ram_16x8k_dp_synth_inst/bmg_port/DOUTB`
26			`TreeUpdate [SetDefaultTree]`
27			`WaveRestoreCursors {{Cursor 1} {0 ps} 0}`
28			`configure wave -namecolwidth 150`
29			`configure wave -valuecolwidth 100`
30			`configure wave -justifyvalue left`
31			`configure wave -signalnamewidth 1`
32			`configure wave -snapdistance 10`
33			`configure wave -datasetprefix 0`
34			`configure wave -rowmargin 4`
35			`configure wave -childrowmargin 2`
36			`configure wave -gridoffset 0`
37			`configure wave -gridperiod 1`
38			`configure wave -griddelta 40`
39			`configure wave -timeline 0`
40			`configure wave -timelineunits ps`
41			`update`
42			`WaveRestoreZoom {0 ps} {9464063 ps}`

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x8k_dp/] [simulation/] [timing/] [wave_mti.do] - Blame information for rev 167