URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [summary.log] - Blame information for rev 167

Line No.	Rev	Author	Line
1	157	olivier.gi
2			`User Configuration`
3			`-------------------------------------`
4			`Algorithm : Minimum_Area`
5	167	olivier.gi	`Memory Type : True_Dual_Port_RAM`
6	157	olivier.gi	`Port A Read Width : 16`
7	167	olivier.gi	`Port B Read Width : 16`
8	157	olivier.gi	`Port A Write Width : 16`
9	167	olivier.gi	`Port B Write Width : 16`
10			`Memory Depth : 8192`
11	157	olivier.gi	`--------------------------------------------------------------`
12
13			`Block RAM resource(s) (9K BRAMs) : 0`
14	167	olivier.gi	`Block RAM resource(s) (18K BRAMs) : 8`
15	157	olivier.gi	`--------------------------------------------------------------`
16			`Clock A Frequency : 100`
17			`Port A Enable Rate : 100`
18			`Port A Write Rate : 50`
19			`----------------------------------------------------------`
20	167	olivier.gi	`Estimated Power for IP : 7.975106 mW`
21	157	olivier.gi	`----------------------------------------------------------`