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"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 292: Assignment to logic_1 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_reset_ctrl.vhd" Line 88: Assignment to logic_1 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match.vhd" Line 93: Assignment to logic_0 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gandx.vhd" Line 104: Assignment to logic_1 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gandx.vhd" Line 105: Assignment to logic_0 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gandx_srl_s6.vhd" Line 102: Using initial value '1' for logic_1 since it is never assigned

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_s6.vhd" Line 64: Using initial value '1' for logic_1 since it is never assigned

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_s6_slice_no_rpm.vhd" Line 62: Using initial value '1' for logic_1 since it is never assigned

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_s6_slice_no_rpm.vhd" Line 63: Using initial value '0' for logic_0 since it is never assigned

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigcond.vhd" Line 120: Assignment to logic_1 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigcond.vhd" Line 110: Net <iCFG_EN_VEC[15]> does not have a driver.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gand.vhd" Line 83: Assignment to logic_1 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_gand.vhd" Line 84: Assignment to logic_0 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_gand_srl_s6_set.vhd" Line 148: Using initial value "111111" for srl_remainder since it is never assigned

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_storage.vhd" Line 183: Assignment to logic_1 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_storage.vhd" Line 184: Assignment to logic_0 ignored, since the identifier is never used

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_s6_ramb9.vhd" Line 130: <ramb8bwer> remains a black-box since it has no binding entity.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trace_buffer.vhd" Line 201: Range is empty (null range)

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 383: Net <iCFG_EN_VEC[15]> does not have a driver.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 384: Net <iCFG_EN_16_0> does not have a driver.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" Line 385: Net <iCFG_EN_16_1> does not have a driver.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 279: Net <iCONTROL_IN[17]> does not have a driver.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" Line 283: Net <iATC_CLKIN> does not have a driver.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila.vhd" line 43: Output port <TRIG_OUT> of the instance <U0> is unconnected or connected to loadless signal.

Input <DATA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG4> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG5> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG6> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG7> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG8> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG9> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG10> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG11> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG12> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG13> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG14> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG15> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/chipscope_ila.vhd" line 1162: Output port <TRIG_OUT> of the instance <I_NO_D.U_ILA> is unconnected or connected to loadless signal.

Signal <iCONTROL_IN<17:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <TRIG_OUT> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <iATC_CLKIN> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <CONTROL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_IN<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_IN<10:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_IN<17:14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CONTROL_IN<34:20>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ATC_CLKIN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 601: Output port <HALT> of the instance <U_RST> is unconnected or connected to loadless signal.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 627: Output port <CFG_TSEQ_DOUT> of the instance <U_TRIG> is unconnected or connected to loadless signal.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 790: Output port <CAP_EXT_TRIGOUT> of the instance <U_G2_SQ.U_CAPCTRL> is unconnected or connected to loadless signal.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_core.vhd" line 874: Output port <WR_TSTAMP_OVERFLOW> of the instance <U_CAPSTOR> is unconnected or connected to loadless signal.

Signal <iCFG_EN_VEC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <iCFG_EN_16_0> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <iCFG_EN_16_1> is used but never assigned. This sourceless signal will be automatically connected to value GND.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_trigger.vhd" line 254: Output port <CFG_DOUT> of the instance <U_TC> is unconnected or connected to loadless signal.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TRIG_RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_16_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_16_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_match_combo.vhd" line 160: Output port <CFG_DOUT> of the instance <U_MU> is unconnected or connected to loadless signal.

Input <CLK_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLK_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_TSEQ_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <iCFG_EN_VEC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CAP_ENDSTATE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <TSTAMP_IN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_16_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_16_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_ila_v1_05_a/ila_cap_ctrl_g2_sq.vhd" line 468: Output port <CFG_DOUT> of the instance <I_SRLT_NE_1.U_WHCMPCE> is unconnected or connected to loadless signal.

Input <TRIGGER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REWIND> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLK_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CFG_EN_VEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WR_TSTAMP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WR_GAP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WR_REWIND> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RD_TSTAMP_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WR_RESET_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_s6_ramb9.vhd" line 374: Output port <DOBDO> of the instance <U_RAMB9> is unconnected or connected to loadless signal.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_s6_ramb9.vhd" line 374: Output port <DOPADOP> of the instance <U_RAMB9> is unconnected or connected to loadless signal.

"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/_bbx/chipscope_lib_v1_03_a/cs_bram_simple_s6_ramb9.vhd" line 374: Output port <DOPBDOP> of the instance <U_RAMB9> is unconnected or connected to loadless signal.

HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.