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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_icon.ncf] - Blame information for rev 157

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NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
#Update Constraints
NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
NET "U0/iSHIFT_OUT" TIG ;
TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;

Line No.	Rev	Author	Line
1	157	olivier.gi	`NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;`
2			`TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;`
3			`#Update Constraints`
4			`NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;`
5			`NET "U0/iSHIFT_OUT" TIG ;`
6			`TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;`
7			`TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;`
8			`TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;`
9			`TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;`

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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_icon.ncf] - Blame information for rev 157