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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_icon.xdc] - Blame information for rev 157

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Line No. Rev Author Line
1 157 olivier.gi
# icon XDC
2
create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}]
3
create_generated_clock -name U_CLK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICON/*/DRCK}] -multiply_by 1 -invert [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/UPDATE}]
4
set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAME =~ */U_ICON/*/SHIFT}]
5
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -setup 2
6
set_multicycle_path -from [get_clocks U_CLK] -to [get_clocks J_CLK] -hold 1
7
set_clock_groups -asynchronous -name cross_jtag_clock_domains -group {J_CLK U_CLK}

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