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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila.asy] - Blame information for rev 157

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Line No. Rev Author Line
1 157 olivier.gi
Version 4
2
SymbolType BLOCK
3
TEXT 32 32 LEFT 4 chipscope_ila
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RECTANGLE Normal 32 32 288 704
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LINE Wide 0 80 32 80
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PIN 0 80 LEFT 36
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PINATTR PinName control[35:0]
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PINATTR Polarity IN
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LINE Normal 0 112 32 112
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PIN 0 112 LEFT 36
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PINATTR PinName clk
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PINATTR Polarity IN
13
LINE Wide 0 176 32 176
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PIN 0 176 LEFT 36
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PINATTR PinName trig0[23:0]
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PINATTR Polarity IN
17
 

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