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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila.cdc] - Blame information for rev 157

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Line No. Rev Author Line
1 157 olivier.gi
#ChipScope Core Generator Project File Version 3.0
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#Tue Sep 25 22:02:47 CEST 2012
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SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
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SignalExport.bus<0000>.name=TRIG0
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SignalExport.bus<0000>.offset=0.0
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SignalExport.bus<0000>.precision=0
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SignalExport.bus<0000>.radix=Bin
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SignalExport.bus<0000>.scaleFactor=1.0
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SignalExport.clockChannel=CLK
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SignalExport.dataEqualsTrigger=true
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SignalExport.triggerChannel<0000><0000>=TRIG0[0]
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SignalExport.triggerChannel<0000><0001>=TRIG0[1]
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SignalExport.triggerChannel<0000><0002>=TRIG0[2]
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SignalExport.triggerChannel<0000><0003>=TRIG0[3]
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SignalExport.triggerChannel<0000><0004>=TRIG0[4]
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SignalExport.triggerChannel<0000><0005>=TRIG0[5]
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SignalExport.triggerChannel<0000><0006>=TRIG0[6]
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SignalExport.triggerChannel<0000><0007>=TRIG0[7]
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SignalExport.triggerChannel<0000><0008>=TRIG0[8]
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SignalExport.triggerChannel<0000><0009>=TRIG0[9]
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SignalExport.triggerChannel<0000><0010>=TRIG0[10]
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SignalExport.triggerChannel<0000><0011>=TRIG0[11]
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SignalExport.triggerChannel<0000><0012>=TRIG0[12]
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SignalExport.triggerChannel<0000><0013>=TRIG0[13]
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SignalExport.triggerChannel<0000><0014>=TRIG0[14]
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SignalExport.triggerChannel<0000><0015>=TRIG0[15]
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SignalExport.triggerChannel<0000><0016>=TRIG0[16]
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SignalExport.triggerChannel<0000><0017>=TRIG0[17]
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SignalExport.triggerChannel<0000><0018>=TRIG0[18]
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SignalExport.triggerChannel<0000><0019>=TRIG0[19]
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SignalExport.triggerChannel<0000><0020>=TRIG0[20]
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SignalExport.triggerChannel<0000><0021>=TRIG0[21]
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SignalExport.triggerChannel<0000><0022>=TRIG0[22]
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SignalExport.triggerChannel<0000><0023>=TRIG0[23]
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SignalExport.triggerPort<0000>.name=TRIG0
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SignalExport.triggerPortCount=1
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SignalExport.triggerPortIsData<0000>=true
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SignalExport.triggerPortWidth<0000>=24
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SignalExport.type=ila
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