URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila.v] - Blame information for rev 157

Line No.	Rev	Author	Line
1	157	olivier.gi	`///////////////////////////////////////////////////////////////////////////////`
2			`// Copyright (c) 2012 Xilinx, Inc.`
3			`// All Rights Reserved`
4			`///////////////////////////////////////////////////////////////////////////////`
5			`// ____ ____`
6			`// / /\/ /`
7			`// /___/ \ / Vendor : Xilinx`
8			`// \ \ \/ Version : 14.2`
9			`// \ \ Application: Xilinx CORE Generator`
10			`// / / Filename : chipscope_ila.v`
11			`// /___/ /\ Timestamp : Tue Sep 25 22:02:47 CEST 2012`
12			`// \ \ / \`
13			`// \___\/\___\`
14			`//`
15			`// Design Name: Verilog Synthesis Wrapper`
16			`///////////////////////////////////////////////////////////////////////////////`
17			`// This wrapper is used to integrate with Project Navigator and PlanAhead`
18
19			`timescale 1ns/1ps
20
21			`module chipscope_ila(`
22			`CONTROL,`
23			`CLK,`
24			`TRIG0);`
25
26
27			`inout [35 : 0] CONTROL;`
28			`input CLK;`
29			`input [23 : 0] TRIG0;`
30
31			`endmodule`