URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila_flist.txt] - Blame information for rev 157

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# Output products list for 
chipscope_ila.asy
chipscope_ila.cdc
chipscope_ila.constraints/chipscope_ila.ucf
chipscope_ila.constraints/chipscope_ila.xdc
chipscope_ila.gise
chipscope_ila.ncf
chipscope_ila.ngc
chipscope_ila.ucf
chipscope_ila.v
chipscope_ila.veo
chipscope_ila.xco
chipscope_ila.xdc
chipscope_ila.xise
chipscope_ila_flist.txt
chipscope_ila_readme.txt
chipscope_ila_xmdf.tcl

Line No.	Rev	Author	Line
1	157	olivier.gi	`# Output products list for`
2			`chipscope_ila.asy`
3			`chipscope_ila.cdc`
4			`chipscope_ila.constraints/chipscope_ila.ucf`
5			`chipscope_ila.constraints/chipscope_ila.xdc`
6			`chipscope_ila.gise`
7			`chipscope_ila.ncf`
8			`chipscope_ila.ngc`
9			`chipscope_ila.ucf`
10			`chipscope_ila.v`
11			`chipscope_ila.veo`
12			`chipscope_ila.xco`
13			`chipscope_ila.xdc`
14			`chipscope_ila.xise`
15			`chipscope_ila_flist.txt`
16			`chipscope_ila_readme.txt`
17			`chipscope_ila_xmdf.tcl`

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila_flist.txt] - Blame information for rev 157