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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila_readme.txt] - Blame information for rev 157

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1 157 olivier.gi 
The following files were generated for 'chipscope_ila' in directory
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/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/
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XCO file generator:
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   Generate an XCO file for compatibility with legacy flows.
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   * chipscope_ila.xco
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Creates an implementation netlist:
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   Creates an implementation netlist for the IP.
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   * chipscope_ila.cdc
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   * chipscope_ila.constraints/chipscope_ila.ucf
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   * chipscope_ila.constraints/chipscope_ila.xdc
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   * chipscope_ila.ncf
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   * chipscope_ila.ngc
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   * chipscope_ila.ucf
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   * chipscope_ila.v
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   * chipscope_ila.veo
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   * chipscope_ila.xdc
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   * chipscope_ila_xmdf.tcl
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IP Symbol Generator:
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   Generate an IP symbol based on the current project options'.
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   * chipscope_ila.asy
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Generate ISE subproject:
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   Create an ISE subproject for use when including this core in ISE designs
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   * chipscope_ila.gise
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   * chipscope_ila.xise
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Deliver Readme:
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   Readme file for the IP.
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   * chipscope_ila_readme.txt
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Generate FLIST file:
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   Text file listing all of the output files produced when a customized core was
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   generated in the CORE Generator.
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   * chipscope_ila_flist.txt
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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