URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [coregen.cgc] - Blame information for rev 157

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   xilinx.com
   CoreGen
   coregen
   1.0
   
      
         chipscope_icon
         
         
            chipscope_icon
            USER1
            false
            false
            false
            1
            external
            false
            true
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            1
            1
            0
            external
            false
            0
            0
            0
            0
            0
            0
            0
            0
            chipscope_icon
            Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  csg324
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2012-07-21+03:11
               
            
            
               
                  apply_current_project_options_generator
               
               
                  customization_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./chipscope_icon.xco
                     xco
                     Tue Sep 25 19:58:22 GMT 2012
                     0x513AA755
                     generationID_4013899584
                  
               
               
                  ngc_netlist_generator
                  
                     ./chipscope_icon.constraints/chipscope_icon.ucf
                     ucf
                     Tue Sep 25 19:59:11 GMT 2012
                     0x4E907B10
                     generationID_4013899584
                  
                  
                     ./chipscope_icon.constraints/chipscope_icon.xdc
                     xdc
                     Tue Sep 25 19:59:11 GMT 2012
                     0x23B3A75F
                     generationID_4013899584
                  
                  
                     ./chipscope_icon.ngc
                     ngc
                     Tue Sep 25 19:59:07 GMT 2012
                     0x26AD7FD7
                     generationID_4013899584
                  
                  
                     ./chipscope_icon.ucf
                     ignore
                     ucf
                     Tue Sep 25 19:59:11 GMT 2012
                     0x4E907B10
                     generationID_4013899584
                  
                  
                     ./chipscope_icon.v
                     verilog
                     verilogSynthesis
                     Tue Sep 25 19:59:11 GMT 2012
                     0x2DD07E02
                     generationID_4013899584
                  
                  
                     ./chipscope_icon.veo
                     veo
                     Tue Sep 25 19:59:11 GMT 2012
                     0x05F4264F
                     generationID_4013899584
                  
                  
                     ./chipscope_icon.xdc
                     ignore
                     xdc
                     Tue Sep 25 19:59:11 GMT 2012
                     0x23B3A75F
                     generationID_4013899584
                  
                  
                     ./chipscope_icon_xmdf.tcl
                     tcl
                     Tue Sep 25 19:58:22 GMT 2012
                     0xA9BCAE1B
                     generationID_4013899584
                  
               
               
                  instantiation_template_generator
               
               
                  asy_generator
                  
                     ./chipscope_icon.asy
                     asy
                     Tue Sep 25 19:59:11 GMT 2012
                     0xEE64DF2A
                     generationID_4013899584
                  
               
               
                  xmdf_generator
               
               
                  ise_generator
                  
                     ./chipscope_icon.gise
                     ignore
                     gise
                     Tue Sep 25 19:59:16 GMT 2012
                     0x2CE4C054
                     generationID_4013899584
                  
                  
                     ./chipscope_icon.xise
                     ignore
                     xise
                     Tue Sep 25 19:59:16 GMT 2012
                     0x244432EF
                     generationID_4013899584
                  
               
               
                  deliver_readme_generator
                  
                     ./chipscope_icon_readme.txt
                     ignore
                     txtReadme
                     txt
                     Tue Sep 25 19:59:16 GMT 2012
                     0xBD31C4B0
                     generationID_4013899584
                  
               
               
                  flist_generator
                  
                     ./chipscope_icon_flist.txt
                     ignore
                     txtFlist
                     txt
                     Tue Sep 25 19:59:16 GMT 2012
                     0xC5079496
                     generationID_4013899584
                  
               
               
                  view_readme_generator
               
            
         
      
      
         chipscope_ila
         
         
            chipscope_ila
            8
            8
            8
            8
            basic_with_edges
            basic_with_edges
            basic_with_edges
            false
            basic_with_edges
            8
            8
            basic_with_edges
            8
            basic_with_edges
            true
            basic_with_edges
            8
            8
            8
            8
            basic_with_edges
            basic_with_edges
            basic_with_edges
            basic_with_edges
            1
            basic_with_edges
            1
            basic_with_edges
            1
            basic_with_edges
            1
            basic_with_edges
            1
            basic_with_edges
            1
            1
            external
            1
            false
            false
            Rising
            Disabled
            Disabled
            true
            Disabled
            Disabled
            Disabled
            Disabled
            Disabled
            0
            false
            false
            1
            1
            1
            1
            1
            1
            1
            8192
            1
            1
            1
            Disabled
            Disabled
            Disabled
            Disabled
            false
            Disabled
            false
            false
            Disabled
            false
            false
            Disabled
            false
            false
            Disabled
            false
            false
            Disabled
            false
            false
            false
            false
            false
            false
            false
            24
            8
            8
            8
            8
            0
            1
            0
            0
            1
            1
            0
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            1
            0
            0
            6
            0
            12
            1
            1
            1
            1
            1
            1
            1
            1
            24
            1
            0
            0
            external
            7
            13
            1
            1
            1
            2
            0
            false
            1
            1
            1
            1
            1
            1
            1
            1
            1
            0
            1
            1
            0
            0
            0
            1
            1
            8
            14
            0
            1
            1
            3
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            9
            chipscope_ila
            15
            0
            Component_Name=chipscope_ila;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=false;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=8192;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=24;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false
            4
            10
            1
            0
            0
            0
            8192
            1
            2
            0
            1
            0
            0
            0
            1
            5
            0
            0
            11
            0
            0
            0
            0
            1
            0
            1
            0
            1
            0
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  csg324
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2012-07-21+03:12
               
            
            
               
                  apply_current_project_options_generator
               
               
                  customization_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./chipscope_ila.xco
                     xco
                     Tue Sep 25 20:00:06 GMT 2012
                     0xF6812BCE
                     generationID_1879581046
                  
               
               
                  ngc_netlist_generator
                  
                     ./chipscope_ila.cdc
                     unknown
                     Tue Sep 25 20:02:47 GMT 2012
                     0x008A59C9
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.constraints/chipscope_ila.ucf
                     ucf
                     Tue Sep 25 20:02:47 GMT 2012
                     0x241A9D00
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.constraints/chipscope_ila.xdc
                     xdc
                     Tue Sep 25 20:02:47 GMT 2012
                     0xF9FF2761
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.ncf
                     ignore
                     unknown
                     Tue Sep 25 20:02:47 GMT 2012
                     0x241A9D00
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.ngc
                     ngc
                     Tue Sep 25 20:02:38 GMT 2012
                     0x6E7A4C11
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.ucf
                     ignore
                     ucf
                     Tue Sep 25 20:02:47 GMT 2012
                     0x241A9D00
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.v
                     verilog
                     verilogSynthesis
                     Tue Sep 25 20:02:47 GMT 2012
                     0xD3503B44
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.veo
                     veo
                     Tue Sep 25 20:02:47 GMT 2012
                     0x6CD58035
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.xdc
                     ignore
                     xdc
                     Tue Sep 25 20:02:47 GMT 2012
                     0xF9FF2761
                     generationID_1879581046
                  
                  
                     ./chipscope_ila_xmdf.tcl
                     tcl
                     Tue Sep 25 20:00:07 GMT 2012
                     0xC99E4D94
                     generationID_1879581046
                  
               
               
                  instantiation_template_generator
               
               
                  asy_generator
                  
                     ./chipscope_ila.asy
                     asy
                     Tue Sep 25 20:02:48 GMT 2012
                     0x8CEFF05F
                     generationID_1879581046
                  
               
               
                  xmdf_generator
               
               
                  ise_generator
                  
                     ./chipscope_ila.gise
                     ignore
                     gise
                     Tue Sep 25 20:02:53 GMT 2012
                     0xBAD08DEE
                     generationID_1879581046
                  
                  
                     ./chipscope_ila.xise
                     ignore
                     xise
                     Tue Sep 25 20:02:53 GMT 2012
                     0xF21B3E1E
                     generationID_1879581046
                  
               
               
                  deliver_readme_generator
                  
                     ./chipscope_ila_readme.txt
                     ignore
                     txtReadme
                     txt
                     Tue Sep 25 20:02:53 GMT 2012
                     0x3FD62AB8
                     generationID_1879581046
                  
               
               
                  flist_generator
                  
                     ./chipscope_ila_flist.txt
                     ignore
                     txtFlist
                     txt
                     Tue Sep 25 20:02:53 GMT 2012
                     0x7BFAD8E1
                     generationID_1879581046
                  
               
               
                  view_readme_generator
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc6slx9
            spartan6
            csg324
            -2
         
         
            BusFormatAngleBracketNotRipped
            Verilog
            true
            Foundation_ISE
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            Verilog
            false
         
      
   

 

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [coregen.cgc] - Blame information for rev 157

Line No.	Rev	Author	Line
1	157	olivier.gi
2
3			`xilinx.com`
4			`CoreGen`
5			`coregen`
6			`1.0`
7
8
9			`chipscope_icon`
10
11
12			`chipscope_icon`
13			`USER1`
14			`false`
15			`false`
16			`false`
17			`1`
18			`external`
19			`false`
20			`true`
21			`1`
22			`1`
23			`0`
24			`0`
25			`0`
26			`0`
27			`0`
28			`0`
29			`0`
30			`0`
31			`0`
32			`1`
33			`1`
34			`0`
35			`external`
36			`false`
37			`0`
38			`0`
39			`0`
40			`0`
41			`0`
42			`0`
43			`0`
44			`0`
45			`chipscope_icon`
46			`Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false`
47
48
49
50
51			`coregen`
52			`./`
53			`./tmp/`
54			`./tmp/_cg/`
55
56
57			`xc6slx9`
58			`spartan6`
59			`csg324`
60			`-2`
61
62
63			`BusFormatAngleBracketNotRipped`
64			`Verilog`
65			`true`
66			`Foundation_ISE`
67			`false`
68			`false`
69			`false`
70			`Ngc`
71			`false`
72
73
74			`Behavioral`
75			`Verilog`
76			`false`
77
78
79			`2012-07-21+03:11`
80
81
82
83
84			`apply_current_project_options_generator`
85
86
87			`customization_generator`
88
89
90			`model_parameter_resolution_generator`
91
92
93			`ip_xco_generator`
94
95			`./chipscope_icon.xco`
96			`xco`
97			`Tue Sep 25 19:58:22 GMT 2012`
98			`0x513AA755`
99			`generationID_4013899584`
100
101
102
103			`ngc_netlist_generator`
104
105			`./chipscope_icon.constraints/chipscope_icon.ucf`
106			`ucf`
107			`Tue Sep 25 19:59:11 GMT 2012`
108			`0x4E907B10`
109			`generationID_4013899584`
110
111
112			`./chipscope_icon.constraints/chipscope_icon.xdc`
113			`xdc`
114			`Tue Sep 25 19:59:11 GMT 2012`
115			`0x23B3A75F`
116			`generationID_4013899584`
117
118
119			`./chipscope_icon.ngc`
120			`ngc`
121			`Tue Sep 25 19:59:07 GMT 2012`
122			`0x26AD7FD7`
123			`generationID_4013899584`
124
125
126			`./chipscope_icon.ucf`
127			`ignore`
128			`ucf`
129			`Tue Sep 25 19:59:11 GMT 2012`
130			`0x4E907B10`
131			`generationID_4013899584`
132
133
134			`./chipscope_icon.v`
135			`verilog`
136			`verilogSynthesis`
137			`Tue Sep 25 19:59:11 GMT 2012`
138			`0x2DD07E02`
139			`generationID_4013899584`
140
141
142			`./chipscope_icon.veo`
143			`veo`
144			`Tue Sep 25 19:59:11 GMT 2012`
145			`0x05F4264F`
146			`generationID_4013899584`
147
148
149			`./chipscope_icon.xdc`
150			`ignore`
151			`xdc`
152			`Tue Sep 25 19:59:11 GMT 2012`
153			`0x23B3A75F`
154			`generationID_4013899584`
155
156
157			`./chipscope_icon_xmdf.tcl`
158			`tcl`
159			`Tue Sep 25 19:58:22 GMT 2012`
160			`0xA9BCAE1B`
161			`generationID_4013899584`
162
163
164
165			`instantiation_template_generator`
166
167
168			`asy_generator`
169
170			`./chipscope_icon.asy`
171			`asy`
172			`Tue Sep 25 19:59:11 GMT 2012`
173			`0xEE64DF2A`
174			`generationID_4013899584`
175
176
177
178			`xmdf_generator`
179
180
181			`ise_generator`
182
183			`./chipscope_icon.gise`
184			`ignore`
185			`gise`
186			`Tue Sep 25 19:59:16 GMT 2012`
187			`0x2CE4C054`
188			`generationID_4013899584`
189
190
191			`./chipscope_icon.xise`
192			`ignore`
193			`xise`
194			`Tue Sep 25 19:59:16 GMT 2012`
195			`0x244432EF`
196			`generationID_4013899584`
197
198
199
200			`deliver_readme_generator`
201
202			`./chipscope_icon_readme.txt`
203			`ignore`
204			`txtReadme`
205			`txt`
206			`Tue Sep 25 19:59:16 GMT 2012`
207			`0xBD31C4B0`
208			`generationID_4013899584`
209
210
211
212			`flist_generator`
213
214			`./chipscope_icon_flist.txt`
215			`ignore`
216			`txtFlist`
217			`txt`
218			`Tue Sep 25 19:59:16 GMT 2012`
219			`0xC5079496`
220			`generationID_4013899584`
221
222
223
224			`view_readme_generator`
225
226
227
228
229
230			`chipscope_ila`
231
232
233			`chipscope_ila`
234			`8`
235			`8`
236			`8`
237			`8`
238			`basic_with_edges`
239			`basic_with_edges`
240			`basic_with_edges`
241			`false`
242			`basic_with_edges`
243			`8`
244			`8`
245			`basic_with_edges`
246			`8`
247			`basic_with_edges`
248			`true`
249			`basic_with_edges`
250			`8`
251			`8`
252			`8`
253			`8`
254			`basic_with_edges`
255			`basic_with_edges`
256			`basic_with_edges`
257			`basic_with_edges`
258			`1`
259			`basic_with_edges`
260			`1`
261			`basic_with_edges`
262			`1`
263			`basic_with_edges`
264			`1`
265			`basic_with_edges`
266			`1`
267			`basic_with_edges`
268			`1`
269			`1`
270			`external`
271			`1`
272			`false`
273			`false`
274			`Rising`
275			`Disabled`
276			`Disabled`
277			`true`
278			`Disabled`
279			`Disabled`
280			`Disabled`
281			`Disabled`
282			`Disabled`
283			`0`
284			`false`
285			`false`
286			`1`
287			`1`
288			`1`
289			`1`
290			`1`
291			`1`
292			`1`
293			`8192`
294			`1`
295			`1`
296			`1`
297			`Disabled`
298			`Disabled`
299			`Disabled`
300			`Disabled`
301			`false`
302			`Disabled`
303			`false`
304			`false`
305			`Disabled`
306			`false`
307			`false`
308			`Disabled`
309			`false`
310			`false`
311			`Disabled`
312			`false`
313			`false`
314			`Disabled`
315			`false`
316			`false`
317			`false`
318			`false`
319			`false`
320			`false`
321			`false`
322			`24`
323			`8`
324			`8`
325			`8`
326			`8`
327			`0`
328			`1`
329			`0`
330			`0`
331			`1`
332			`1`
333			`0`
334			`1`
335			`0`
336			`0`
337			`0`
338			`0`
339			`0`
340			`0`
341			`0`
342			`0`
343			`0`
344			`0`
345			`1`
346			`0`
347			`0`
348			`6`
349			`0`
350			`12`
351			`1`
352			`1`
353			`1`
354			`1`
355			`1`
356			`1`
357			`1`
358			`1`
359			`24`
360			`1`
361			`0`
362			`0`
363			`external`
364			`7`
365			`13`
366			`1`
367			`1`
368			`1`
369			`2`
370			`0`
371			`false`
372			`1`
373			`1`
374			`1`
375			`1`
376			`1`
377			`1`
378			`1`
379			`1`
380			`1`
381			`0`
382			`1`
383			`1`
384			`0`
385			`0`
386			`0`
387			`1`
388			`1`
389			`8`
390			`14`
391			`0`
392			`1`
393			`1`
394			`3`
395			`1`
396			`0`
397			`0`
398			`0`
399			`0`
400			`0`
401			`0`
402			`0`
403			`0`
404			`0`
405			`0`
406			`0`
407			`0`
408			`0`
409			`0`
410			`0`
411			`0`
412			`0`
413			`0`
414			`0`
415			`9`
416			`chipscope_ila`
417			`15`
418			`0`
419			Component_Name=chipscope_ila;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=1;Use_RPMs=false;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=8192;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=24;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=8;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic_with_edges;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=8;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic_with_edges;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=8;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic_with_edges;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=8;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic_with_edges;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=8;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic_with_edges;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=8;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic_with_edges;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=8;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic_with_edges;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=8;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic_with_edges;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=8;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic_with_edges;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=8;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic_with_edges;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=8;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic_with_edges;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=8;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic_with_edges;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=8;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic_with_edges;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=8;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic_with_edges;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=8;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic_with_edges;Exclude_From_Data_Storage_16=false
420			`4`
421			`10`
422			`1`
423			`0`
424			`0`
425			`0`
426			`8192`
427			`1`
428			`2`
429			`0`
430			`1`
431			`0`
432			`0`
433			`0`
434			`1`
435			`5`
436			`0`
437			`0`
438			`11`
439			`0`
440			`0`
441			`0`
442			`0`
443			`1`
444			`0`
445			`1`
446			`0`
447			`1`
448			`0`
449			`0`
450			`0`
451			`0`
452			`0`
453			`0`
454			`0`
455
456
457
458
459			`coregen`
460			`./`
461			`./tmp/`
462			`./tmp/_cg/`
463
464
465			`xc6slx9`
466			`spartan6`
467			`csg324`
468			`-2`
469
470
471			`BusFormatAngleBracketNotRipped`
472			`Verilog`
473			`true`
474			`Foundation_ISE`
475			`false`
476			`false`
477			`false`
478			`Ngc`
479			`false`
480
481
482			`Behavioral`
483			`Verilog`
484			`false`
485
486
487			`2012-07-21+03:12`
488
489
490
491
492			`apply_current_project_options_generator`
493
494
495			`customization_generator`
496
497
498			`model_parameter_resolution_generator`
499
500
501			`ip_xco_generator`
502
503			`./chipscope_ila.xco`
504			`xco`
505			`Tue Sep 25 20:00:06 GMT 2012`
506			`0xF6812BCE`
507			`generationID_1879581046`
508
509
510
511			`ngc_netlist_generator`
512
513			`./chipscope_ila.cdc`
514			`unknown`
515			`Tue Sep 25 20:02:47 GMT 2012`
516			`0x008A59C9`
517			`generationID_1879581046`
518
519
520			`./chipscope_ila.constraints/chipscope_ila.ucf`
521			`ucf`
522			`Tue Sep 25 20:02:47 GMT 2012`
523			`0x241A9D00`
524			`generationID_1879581046`
525
526
527			`./chipscope_ila.constraints/chipscope_ila.xdc`
528			`xdc`
529			`Tue Sep 25 20:02:47 GMT 2012`
530			`0xF9FF2761`
531			`generationID_1879581046`
532
533
534			`./chipscope_ila.ncf`
535			`ignore`
536			`unknown`
537			`Tue Sep 25 20:02:47 GMT 2012`
538			`0x241A9D00`
539			`generationID_1879581046`
540
541
542			`./chipscope_ila.ngc`
543			`ngc`
544			`Tue Sep 25 20:02:38 GMT 2012`
545			`0x6E7A4C11`
546			`generationID_1879581046`
547
548
549			`./chipscope_ila.ucf`
550			`ignore`
551			`ucf`
552			`Tue Sep 25 20:02:47 GMT 2012`
553			`0x241A9D00`
554			`generationID_1879581046`
555
556
557			`./chipscope_ila.v`
558			`verilog`
559			`verilogSynthesis`
560			`Tue Sep 25 20:02:47 GMT 2012`
561			`0xD3503B44`
562			`generationID_1879581046`
563
564
565			`./chipscope_ila.veo`
566			`veo`
567			`Tue Sep 25 20:02:47 GMT 2012`
568			`0x6CD58035`
569			`generationID_1879581046`
570
571
572			`./chipscope_ila.xdc`
573			`ignore`
574			`xdc`
575			`Tue Sep 25 20:02:47 GMT 2012`
576			`0xF9FF2761`
577			`generationID_1879581046`
578
579
580			`./chipscope_ila_xmdf.tcl`
581			`tcl`
582			`Tue Sep 25 20:00:07 GMT 2012`
583			`0xC99E4D94`
584			`generationID_1879581046`
585
586
587
588			`instantiation_template_generator`
589
590
591			`asy_generator`
592
593			`./chipscope_ila.asy`
594			`asy`
595			`Tue Sep 25 20:02:48 GMT 2012`
596			`0x8CEFF05F`
597			`generationID_1879581046`
598
599
600
601			`xmdf_generator`
602
603
604			`ise_generator`
605
606			`./chipscope_ila.gise`
607			`ignore`
608			`gise`
609			`Tue Sep 25 20:02:53 GMT 2012`
610			`0xBAD08DEE`
611			`generationID_1879581046`
612
613
614			`./chipscope_ila.xise`
615			`ignore`
616			`xise`
617			`Tue Sep 25 20:02:53 GMT 2012`
618			`0xF21B3E1E`
619			`generationID_1879581046`
620
621
622
623			`deliver_readme_generator`
624
625			`./chipscope_ila_readme.txt`
626			`ignore`
627			`txtReadme`
628			`txt`
629			`Tue Sep 25 20:02:53 GMT 2012`
630			`0x3FD62AB8`
631			`generationID_1879581046`
632
633
634
635			`flist_generator`
636
637			`./chipscope_ila_flist.txt`
638			`ignore`
639			`txtFlist`
640			`txt`
641			`Tue Sep 25 20:02:53 GMT 2012`
642			`0x7BFAD8E1`
643			`generationID_1879581046`
644
645
646
647			`view_readme_generator`
648
649
650
651
652
653
654
655
656			`coregen`
657			`./`
658			`./tmp/`
659			`./tmp/_cg/`
660
661
662			`xc6slx9`
663			`spartan6`
664			`csg324`
665			`-2`
666
667
668			`BusFormatAngleBracketNotRipped`
669			`Verilog`
670			`true`
671			`Foundation_ISE`
672			`false`
673			`false`
674			`false`
675			`Ngc`
676			`false`
677
678
679			`Behavioral`
680			`Verilog`
681			`false`
682
683
684
685
686